Experiences Developing the OpenUH Compiler and Runtime Infrastructure

Chapman, Barbara; Eachempati, Deepak; Hernández, Óscar

doi:10.1007/s10766-012-0230-9

Cited by 17 publications

(4 citation statements)

References 36 publications

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“…We plan, as future work, to automate the methodology we describe in this paper, translating communication calls into load/store instructions, in the OpenUH [9] compiler to optimize OpenSHMEM programs for Xeon Phi and shared memory platforms more generally. This work was supported in part by the United States Department of Defense and used resources of the Extreme Scale Systems Center at Oak Ridge National Laboratory.…”

Section: Resultsmentioning

confidence: 99%

Native Mode-Based Optimizations of Remote Memory Accesses in OpenSHMEM for Intel Xeon Phi

Namashivayam

Ghosh

Khaldi

et al. 2014

Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models

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OpenSHMEM is a PGAS library that aims to deliver high performance while retaining portability. Communication operations are a major obstacle to scalable parallel performance and are highly dependent on the target architecture. However, to date there has been no work on how to efficiently support OpenSHMEM running natively on Intel Xeon Phi, a highly-parallel, power-efficient and widely-used many-core architecture. Given the importance of communication in parallel architectures, this paper describes a novel methodology for optimizing remote-memory accesses for execution of OpenSHMEM programs on Intel Xeon Phi processors.In native mode, we can exploit the Xeon Phi shared memory and convert OpenSHMEM one-sided communication calls into local load/store statements using the shmem_ptr routine. This approach makes it possible for the compiler to perform essential optimizations for Xeon Phi such as vectorization. To the best of our knowledge, this is the first time the impact of shmem_ptr is analyzed thoroughly on a manycore system. We show the benefits of this approach on the PGAS-Microbenchmarks we specifically developed for this research. Our results exhibit a decrease in latency for onesided communication operations by up to 60% and increase in bandwidth by up to 12x. Moreover, we study different reduction algorithms and exploit local load/store to optimize data transfers in these algorithms for Xeon Phi which permits improvement of up to 22% compared to MVAPICH and up to 60% compared to Intel MPI. Apart from microbenchmarks, experimental results on NAS IS and SP benchmarks show that performance gains of up to 20x are possible.

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Section: Resultsmentioning

confidence: 99%

Native Mode-Based Optimizations of Remote Memory Accesses in OpenSHMEM for Intel Xeon Phi

Namashivayam

Ghosh

Khaldi

et al. 2014

Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models

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“…Perhaps the best known example is the Open64 compiler's WHIRL IR. Despite now being effectively discontinued, Open64 has at least until recently used as both a research platform in compiler and computer-architecture research [3], and as the basis of proprietary compilers [1,15,18], and so remains relevant today. WHIRL encompasses five distinct IRs, ranging from the Very High WHIRL that is very much like an AST; through target-independent High WHIRL and largely target-independent Mid WHIRL; to Low and Very Low WHIRL that roughly correspond to conventional target-dependent assembly language and machine code, respectively.…”

Section: Open64mentioning

confidence: 99%

The ARES High-level Intermediate Representation

Moss

2017

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The LLVM intermediate representation (IR) lacks semantic constructs for depicting common high-performance operations such as parallel and concurrent execution, communication and synchronization. Currently, representing such semantics in LLVM requires either extending the intermediate form (a significant undertaking) or the use of ad hoc indirect means such as encoding them as intrinsics and/or the use of metadata constructs. In this paper we discuss a work in progress to explore the design and implementation of a new compilation stage and associated high-level intermediate form that is placed between the abstract syntax tree and when it is lowered to LLVM's IR. This highlevel representation is a superset of LLVM IR and supports the direct representation of these common parallel computing constructs along with the infrastructure for supporting analysis and transformation passes on this representation.

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“…We have implemented support for coarrays in OpenUH [3] [4], an open-source research compiler based on the Open64 compiler suite. CAF support in OpenUH comprises three areas: (1) an extended front-end that accepts the coarray syntax and related intrinsic functions/subroutines, (2) back-end translation, optimization, and code generation, and (3) a portable runtime library that can be deployed on a variety of HPC platforms.…”

Section: Caf Implementationmentioning

confidence: 99%