Executing synchronous dataflow graphs on a SPM-based multicore architecture

Abstract

In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a nonoptimized approach and the previous approach.

Task-FIFO Co-Scheduling of Streaming Applications on MPSoCs with Predictable Memory Hierarchy

“…We adapt HAFF to our problem and use it as a comparison in this paper to justify the importance of FIFO allocation and the effectiveness of our ITFCS algorithm. While the above works use DAGs, recently, [24], [25] investigate similar problems for SDFGs. [24] researches how to use the SPM of a single-processor machine to overlay the task code of the application modeled by an SDFG such that the execution cost of the application is minimized.…”

“…[24] researches how to use the SPM of a single-processor machine to overlay the task code of the application modeled by an SDFG such that the execution cost of the application is minimized. This work is extended by [25] to multiprocessors and data overlay. However, these two works consider dynamic memory overlay, differing from FIFO allocation considered in this paper, which is in fact a kind of static allocation.…”

Scheduling real-time systems with cyclic dependence using data criticality

“…1 Load the dependence graph G; 2 Cycles = simple cycles in G; 3 for cycle in Cycles do 4 for edge in cycle do 5 Calculate probability of error propagation P r(A i = 1) from component tx; 6 Assign probability to edge weights ω ij (tx) ;…”

“…The authors of [30] presented a modular approach to analyze system performance that was applied directly to a cyclic SDF. The scheduling of an SDF was optimized in [6] using evolutionary techniques by considering the limitation of the size of the scratchpad memory. Although these approaches yielded good results, this model decreases the scope of approaches that study real-time systems since it excludes approaches based on DAGs.…”

MPMAP : A high level synthesis and mapping tool for MPSoCs

“…Different task mapping techniques have been developed to optimize the computing performance [3], lifetime reliability [4], and energy consumption [5]. Different methodologies have been used based on simulated annealing (SA) [6], Tabu search (TS) [7], Genetic Algorithms (GA) [8], and Integer linear Programming (ILP) [9]- [11]. The proposed methodologies include both design time techniques [5], [12], and run time mapping techniques [5], [13].…”