Exceeding the dataflow limit via value prediction

Abstract

Meanwhile, numerous mechanisms have been proposed and implemented to eliminate false data dependences and tolerate the latencies induced by true data dependences by allowing instructions to execute out of program order (see [8] for an overview).Surprisingly, in light of the extensive energies focused on eliminating control-flow restrictions on parallel instruction issue, less attention has been paid to eliminating data-flow restrictions on parallel issue. Recent work has focused primarily on reducing the latency of specific types of instructions (usually loads from memory) by rearranging pipeline stages [9,10], initiating memory accesses earlier [11], or speculating that dependences to earlier stores do not exist [12,13,14,15].The most relevant prior work in the area of eliminating data-flow dependences consists of the Tree Machine [16,17], which uses a value cache to store and look up the results of recurring arithmetic expressions to eliminate redundant computation (the value cache, in effect, performs common subexpression elimination [1] in hardware). Richardson follows up on this concept in [18] by introducing the concepts of trivial computation, which is defined as the trivialization of potentially complex operations by the occurrence of simple operands; and redundant computation, where an operation repeatedly performs the same computation because it sees the same operands. He proposes a hardware mechanism (the result cache) which reduces the latency of such trivial or redundant complex arithmetic operations by storing and looking up their results in the result cache.

Value Prediction and Speculative Execution on GPU

“…To overcome this problem, several studies have proposed data value prediction techniques to speculatively break data dependency and improve and exploit ILP: Lipasti et al [3] introduced the basic design of value predictors in the context of superscalar architectures. Sazeides et al [4] demonstrated that different value prediction mechanisms can achieve prediction accuracies ranging from 56 to 92% and result in performance gains ranging from 7 to 23%.…”

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

“…Traditional value prediction overcomes the limits imposed by true dependencies by executing instructions with true dependencies in parallel [12,18]. This technique can also hide instructions with long execution latencies.…”

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

“…Data value speculation has been proposed as a way of overcoming true dependences, further increasing the available parallelism [15], [33].…”