Exact wirelength of hypercubes on a grid

Manuel, Paul; Rajasingh, Indra; Rajan, Bharati; Mercy, Helda

doi:10.1016/j.dam.2008.09.013

Cited by 81 publications

(65 citation statements)

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“…Minimum congestion has been obtained for embedding hypercubes into 2 -dimensional grid [12] and n -dimensional grid [28]. In this section we consider cylinder as host graph, obtain congestion on an edge cut and use it to show that the bound obtained from Edge Congestion Lemma is tight.…”

Section: Resultsmentioning

confidence: 98%

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A Tight Bound for Congestion of an Embedding

Manuel

Rajasingh

Rajan

et al. 2015

Algorithms and Discrete Applied Mathematics

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Abstract. Graph embedding has been known as a powerful tool for implementation of parallel algorithms or simulation of different interconnection networks. Congestion is one of the main optimization objectives in global routing. In this paper, we introduce a technique to obtain a tight bound for congestion of an embedding. Moreover, we give algorithms to compute exact congestion of embedding the hypercubes into the cylinder and the torus and prove that the bound obtained is sharp.

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Section: Resultsmentioning

confidence: 98%

“…The hypercube embedding problem is the problem of mapping a communication graph into a hypercube multiprocessor. Hypercubes are known to simulate other structures such as grids and binary trees [12,13].…”

Section: Introductionmentioning

confidence: 99%

A Tight Bound for Congestion of an Embedding

Manuel

Rajasingh

Rajan

et al. 2015

Algorithms and Discrete Applied Mathematics

Self Cite

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“…Where |T| = r |V (G1)| −2 |E (G1) by Lemma 2 in [9]. Therefore, ECfm is monophonic as G1 is maximum in G. The edge cuts Ej, j = 1, 2, p form a partition in H. Thus, we write …”

Section: Proposition 24: For Embeddings F : G → H and The Monophonicmentioning

confidence: 99%

“…If we find an embedding of G into H which produces the minimum wirelength WL(G, H), such problem is called the wirelength problem "as stated in [9]". We use definitions, Lemmas and Theorems from [1], [2], [5], [6], [7], [8] and [9] for this work.…”

Section: Introductionmentioning

confidence: 99%

“…1) f is a bijective map from V (G) → V (H) 2) f is a one-to-one map from E(G) to {Pf (f (u), f (v)) : Pf (f(u), f(v)) is a path in H between f (u) and f (v) for (u, v) ∈E(G)} "as defined in [8,9]. i.e., The embedding f of G to H is a bijective mapping from the vertex set of G to the vertex set of H and every edge (u, v)  E(G) is mapped to a path between f (u) and f (v) in H. The edge congestion of an embedding f of G into H is the maximum number of edges of the graph G that are embedded on any single edge of H. The wirelength of an embedding f of G into H is given by…”

Section: Introductionmentioning

confidence: 99%

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Monophonic wirelength on Circulant Networks

Samundesvari¹,

Michael²

2018

IJET

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In this paper, we define the monophonic embedding of graph G into graph H and we present an algorithm for finding the monophonic wirelength of circulant networks into the family of grids M(n×2), n≥2.The monophonic embedding of a graph G into a graph H is an embedding denoted by fm is a bijective map from the vertex set of G into the vertex set of H and fm is a one-one mapping from the edge set (x, y) of G into Pm(H) where Pm(H) is the set of monophonic paths between fm(x) and fm(y) for every fm(x), fm(y) H. The monophonic wirelength of fm of G into H is the sum of distances of monophonic paths between two vertices fm(x) and fm(y) in H such that (x, y) E(G). This paper presents a monophonic algorithm to find the monophonic wirelength of circulant networks G(2n, ±S) , where S  {1,2,3,…,n} into the family of grids M[n×2],n≥2. We also derived a Lemma to get the monophonic edge congestion MEC (G,H).

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Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

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Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

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Exact wirelength of hypercubes on a grid

Cited by 81 publications

References 20 publications

A Tight Bound for Congestion of an Embedding

A Tight Bound for Congestion of an Embedding

Monophonic wirelength on Circulant Networks

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

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