Exact two-level minimization of hazard-free logic with multiple-input changes

Removal of resetting of transitions for asynchronous FSM

“…In addition, the resulting combinational implementations, 2 level AND-OR and gC equations, may have more literals because of increased signal arrival orders of reshuffled transitions. According to all our testing cases, the gC implementations have a better chance to reduce the impact of these overhead since a large group of transitions fall in the "state holding" sets instead of on-set and off-set during the hazard-free minimization process [6].…”

Espresso-HF

“…This paper considers combinational circuits having arbitrary finite gate and wire delays (unbounded wire delay model [9]). A pure delay model is assumed as well (see [11]).…”

“…If a transition has a function hazard, no implementation of the function is guaranteed to avoid a glitch during the transition, assuming arbitrary gate and wire delays [9,11]. Therefore, we consider only transitions which are free of function hazards.…”

“…In synchronous design, the development and implementation of CAD packages has been critical to the success of modern automated digital design. In asynchronous design, much progress has been made, including tools for: exact hazard-free two-level logic minimization [9], optimal state assignment [2] and synthesis-for-testability [8]. However, these tools have been limited in handling large-scale designs.…”

“…The material of this section focuses on hazards and hazard-free logic minimization, and is taken from [2] and [9]. For simplicity, we focus on single-output functions.…”