Ex Situ Transfer of Bayesian Neural Networks to Resistive Memory‐Based Inference Hardware

Abstract

In recent years, neural network models [1] have demonstrated human-level competency in multiple tasks, such as pattern recognition, [2] game playing, [3] and strategy development. [4] This progress has led to the promise that a new generation of intelligent computing systems could be applied to such high-complexity tasks at the edge. [5] However, the current generation of edge computing hardware cannot support the energetic demands nor the data volume required to train and adapt such neural network models locally at the edge. [6,7] One solution is ex situ training: a software model is trained on a cloud computing platform and then subsequently transferred onto a hardware system that acts only to perform inference. [8,9] The engine room of such inference hardware is the dot-product (multiply-and-accumulate) operation that is ubiquitous in machine learning. Non-von Neumann dot-product implementations based on nonvolatile resistive random access memory (RRAM) [10][11][12][13] technologies, otherwise known as memristors, are a particularly promising path toward reducing the energy required during inference. Here, the dot product between an input voltage vector and an array of RRAM conductance states, storing the parameters of the model, can be evaluated in-memory through the physics of Ohm's and Kirchhoff m's laws-obviating the need to transfer information on-chip. [14,15] In these systems, however, intrinsic cycle-to-cycle and device-to-device conductance variability constitute a considerable challenge. This random variability constrains the number of separable multilevel conductance states that can be achieved, preventing the high-precision transfer of the model parameters in a single programming step. To mitigate against this variability, iterative closed-loop programming schemes (also referred to as program-verify schemes) are often used, whereby devices are repeatedly programmed until their conductance falls within a discretized window of tolerated error. However, such approaches entail costly circuit overheads as well as energy and time during model transfer. [16][17][18] Other approaches propose to use multiple one-transistor-one-resistor (1T1R) structures in parallel at each array cross-point, [19][20][21] which, although allow for a higher precision in the transferred weight, entail additional costs in area and transfer energy. Other approaches propose to sidestep intrinsic randomness altogether through the quantization of conductance levels into one of either a low-conductance state (LCS) or a highconductance state (HCS) in binarized neural networks. [22] However, such models require a significantly higher number of neuron elements and model parameters to approach the performance of conventional neural networks. [23] The reality is that the programming of resistive memory is an inherently random process, and the devices, therefore, are not well suited to being treated as deterministic quantities.

Two-dimensional materials-based probabilistic synapses and reconfigurable neurons for measuring inference uncertainty using Bayesian neural networks

“…In contrast, here we use cycle-to-cycle variation in the programmability of our MoS 2 memtransistor to generate GRNs. While cycle-to-cycle variation is undesirable for traditional computing, it can be exploited to reduce the design complexity of a BNN accelerator 21 , 22 , 43 . To demonstrate the effect of programming on variation, we use dynamic programming on 40 MoS 2 memtransistors, where we measure the transfer characteristics with different sweep ranges.…”

HfO2-based resistive switching memory devices for neuromorphic computing

“…A key limitation of RRAM devices for hardware ANN implementation is the limited precision due to the program/read variations [68,70]. Such variations can be turned into a precious feature in stochastic computing circuits, e.g., true random number generators [109,110], Bayesian neural networks [108] and Monte Carlo Markov chains [111]. In a Bayesian neural network (figure 11(a)), synaptic parameters usually consist of random variables, which well match the random nature of RRAM conductance obtained without programverify algorithms [108].…”

“…Such variations can be turned into a precious feature in stochastic computing circuits, e.g., true random number generators [109,110], Bayesian neural networks [108] and Monte Carlo Markov chains [111]. In a Bayesian neural network (figure 11(a)), synaptic parameters usually consist of random variables, which well match the random nature of RRAM conductance obtained without programverify algorithms [108]. Figure 11(a) shows the methodology for describing a given probability distribution of weights with stochastic RRAMs: the distribution can be approximated by a combination of a number of Gaussian distributions, each obtained by programming RRAM devices with a fixed pulsed amplitude and time, without verify.…”

“…To represent a single probability distribution, a relatively large number of devices (e.g., 1024) would be required, as opposed to the single RRAM device (or two RRAM devices in the case of a differential synapse) required for describing a fixed, non-probabilistic weight in an ANN. The output neuron distribution can be obtained in figure 11(c) by sampling multiple output results from predefined sub-sets of the RRAM synapses [108]. Similarly, probabilistic Monte Carlo Markov chains were demonstrated by harnessing the stochastic distributions of programmed RRAM conductance, thus taking advantage of the cycle-to-cycle and device-to-device variations of RRAM [111].…”

Best Practices for the Deployment of Edge Inference: The Conclusions to Start Designing

“…Renesas [102] Dynamically Reconfigurable Processor (DRP) technology is special purpose hardware that accelerates image processing algorithms by as much as 10×, or more Recently, resistive memory based Bayesian neural networks have been found applicable in edge inference hardware. In [103], Dalgaty et al propose to use trained Bayesian models with probabilistic programming methods to overcome the inherently random process. Hence, the intrinsic cycle to cycle and device to device conductance variation are limited.…”