Evolvable hardware chips and their applications

Sakanashi, Hidenori; Iwata, Masaya; Keymulen, D.; Murakawa, Masahiro; Kajitani, Isamu; Tanaka, Masaharu; Higuchi, Tetsuya

doi:10.1109/icsmc.1999.815613

Cited by 10 publications

(3 citation statements)

References 11 publications

(1 reference statement)

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“…They have implemented an adaptive prosthetic hand controller [84,85] that can adapt to the user's electromyographic signals in less than 10 minutes with a much more compact circuit than required with a neural network (before that, the user had to adapt to the hand instead of the hand to the user, requiring more than a month of training). They have also evolved data compressors for electrophotographic printing [86,87], often attaining compression ratios twice those obtained with international standard compression algorithms such as Lempel-Ziv, JBIG, and JBIG2. It must be noted that Higuchi's applications often finish as part of a commercial product.…”

Section: Custom Evolvable Fpgasmentioning

confidence: 99%

Verification Techniques for System-Level Design

Fujita¹,

Ghosh²,

Prasad³

2008

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Section: Custom Evolvable Fpgasmentioning

confidence: 99%

Verification Techniques for System-Level Design

Fujita¹,

Ghosh²,

Prasad³

2008

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“…It is based on designing or transforming a circuit by using evolutionary techniques [1], i.e. an evolvable algorithm (EA) controls the generation of new circuits.…”

Section: Introductionmentioning

confidence: 99%

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Gallego¹,

Mora²,

Otero³

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

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“…If circuit design is the goal of an evolutionary algorithm and the fitness function is somewhat related to the functionality to be achieved by the circuit, then the system is referred as evolvable hardware [3] [4]. It may be used off-line, as an alternative to traditional design tools, although for autonomous systems, it is far more attractive the on-line version, where the design is, at its utmost level of autonomy, providing additional capabilities such as self-adaptiveness or self-healing.…”

Section: Introductionmentioning

confidence: 99%

A scalable evolvable hardware processing array

Gallego

Mora

Otero

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Abstract-Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits selfadaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

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Evolvable hardware chips and their applications

Cited by 10 publications

References 11 publications

Verification Techniques for System-Level Design

Verification Techniques for System-Level Design

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

A scalable evolvable hardware processing array

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