Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays

Otero

2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

et al. 2015

Abstract-Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit.Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations.This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks.The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80 000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time.

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Section: A Interconnection Topologiesmentioning

confidence: 99%

Section: Sae = 2 /_ \Aij -T>ij\mentioning

confidence: 99%

Section: B Processing Element Descriptionmentioning

confidence: 99%

Section: B Processing Element Descriptionmentioning

confidence: 99%

Section: Evolutionary Algorithmmentioning

confidence: 99%

See 3 more Smart Citations

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Otero

2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

et al. 2015

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On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

Salvador

Genet Program Evolvable Mach

2018

Evolvable hardware allows generating circuits adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources.The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs.In this article, two different topologies-systolic array (SA) and Cartesian genetic programming (CGP)-are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied.Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10×10 SA has better performance than 5×10 CGP, but uses 50% fewer resources.

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Accelerating the evolution of a systolic array-based evolvable hardware system

Microprocessors and Microsystems

2018