Evolutionary Design of Gate-Level Polymorphic Digital Circuits

Sekanina, Lukáš

doi:10.1007/978-3-540-32003-6_19

Cited by 35 publications

(33 citation statements)

References 6 publications

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“…The related literature spans this area from offline evolution of fault-tolerant circuits able to withstand defects in silicon [3] without increasing circuit's size significantly [4] or compensating supply voltage drifts [5] by recurrent re-evolution after a series of deteriorating events as the wide-band temperature changes or radiation beams treatments [6,7].…”

Section: Introductionmentioning

confidence: 99%

Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture

Knieper

Kaufmann

Glette

et al. 2010

Evolvable Systems: From Biology to Hardware

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Abstract. The evolvable hardware paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degrading effects in the computational resources. Extending these scenarios, we study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, we leverage the Functional Unit Row (FUR) architecture, a coarse-grained reconfigurable classifier, and apply it to two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. We show that FUR's classification performance remains high during changes of the utilized chip area and that performance drops are quickly compensated for. Additionally, we demonstrate that FUR's recovery capability benefits from extra resources.

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Section: Introductionmentioning

confidence: 99%

Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture

Knieper

Kaufmann

Glette

et al. 2010

Evolvable Systems: From Biology to Hardware

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“…Examples of polymorphic gates are available in literature [12], [14], [13]. It was shown that it is possible to consider polymorphic gates as standard building blocks and to use them, together with ordinary gates, to design multifunctional digital circuits [9]. These multifunctional circuits exhibit interesting behaviors not visible in standard digital circuits.…”

Section: Introductionmentioning

confidence: 99%

“…These multifunctional circuits exhibit interesting behaviors not visible in standard digital circuits. A circuit exists that operates as an adder in case that Vdd = 3.3V and as a multiplier in case that Vdd = 1.8V [9]. Its topology is invariable; the only feature which is changed with Vdd is the functionality of some gates.…”

Section: Introductionmentioning

confidence: 99%

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Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules

Sekanina

Martínek

Gajda

2006 IEEE International Conference on Evolutionary Computation

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Abstract-Multifunctional digital circuits are circuits composed of polymorphic (multifunctional) gates. In addition to its standard logic function (such as NAND), a polymorphic gate exhibits another logic function (such as NOR) which is activated under a specific condition, for example, when Vdd, temperature or illumination reaches a certain level. This paper describes the evolutionary design of multifunctional combinational circuits at the gate level using a circuit simulator and in a field programmable gate array (FPGA). The FPGAbased implementation exhibits a significant speedup against a highly optimized software simulator.

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“…Stoica et al introduced an evolutionary approach for the design of polymorphic gates at the transistor level. Sekanina proposed a method for the evolutionary design of gatelevel digital polymorphic circuits in which polymorphic gates are considered as building blocks [8]. In his paper, Miller's cartesian genetic programming was applied.…”

Section: Introductionmentioning

confidence: 99%

Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study

Bidlo

Vašíček

Evolvable Systems: From Biology to Hardware

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Abstract. Cellular automata-based evolutionary development is presented for the design of single-function and polymorphic (two-function) combinational circuits. The impact of evolution of the cellular automaton initial state on the success rate of the evolved solutions is investigated. The experiments show that it is more suitable to fix a proper initial state in order to increase the successfulness and speed of evolution. The proposed developmental model is capable to design a wide range of both single-function and polymorphic circuits.

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Evolutionary Design of Gate-Level Polymorphic Digital Circuits

Cited by 35 publications

References 6 publications

Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture

Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture

Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules

Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study

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