EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoC

Wang, Peng; Niknam, Sobhan; Ma, Shaoping; Wang, Zhiying; Stefanov, Todor

doi:10.1109/dsd.2019.00027

Cited by 3 publications

(4 citation statements)

References 22 publications

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“…Wang et al [4] they work on express virtual channel for power consuming. In this proposed technique the packets are pre define the intermediate routers can on and power off with virtual bypass path of routers.…”

Section: The Low Power With Virtual Channel Techniquesmentioning

confidence: 99%

Low power network on chip architectures: A survey

Muhammad Raza Naqvi

2021

Comput Sci Inf Technol

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Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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Section: The Low Power With Virtual Channel Techniquesmentioning

confidence: 99%

Low power network on chip architectures: A survey

Muhammad Raza Naqvi

2021

Comput Sci Inf Technol

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“…Moreover, through share of packets when to the bypass intake. They method can be largest achievement is berth superpower intake under with towering traffic workloads [4]. Dong Xiang et.al, proposed a work low power fully adaptive routing algorithm for the virtual cut concluded wormhole switched networks on chip.…”

Section: The Low Power With Virtual Channel Techniquesmentioning

confidence: 99%

“…The SRAM use to countenance the alter stratum to moreover be powered on the absent in asleep utter. When SST-RAM are superior in Virtual channels are control when its harsh [4].…”

Section: The Low Power With Virtual Channel Techniquesmentioning

confidence: 99%

“…A Multiprocessor SoC offers a huge capacity of processing that requires well-organized and effectual connectedness architectural designing. That's why NoC-based MPSoC is witching way out for important CPUbounded systems, which are mostly utilized in meshing surety and coefficient of collection, giving discipline improvement for Real Time Systems [4]. Main functioning in network transmission is buffering, and its size optimization has become a good research task for scholars.…”

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confidence: 99%

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Low power network on chip architectures: A survey

Naqvi

2020

Comput. Sci. Inf. Technol.

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Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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DBU-PG: energy-efficient noc design using dual-buffering power gating

Ouyang,

Cao,

et al. 2024

J Supercomput

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EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoC

Cited by 3 publications

References 22 publications

Low power network on chip architectures: A survey

Low power network on chip architectures: A survey

Low power network on chip architectures: A survey

DBU-PG: energy-efficient noc design using dual-buffering power gating

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