Evaluation of memory built-in self repair techniques for high defect density technologies

Anghel, Lorena; Achouri, N.; Nicolaidis, M.

doi:10.1109/prdc.2004.1276581

Cited by 5 publications

(3 citation statements)

References 15 publications

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“…The organization of a testable and repairable memory array equipped with a BISD/BIST diagnostic module, a BIRA module for allocating spare elements, and a BISR circuit for reconfiguring decoders and peripheral memory circuits. Some simulation tools for evaluating the e ciency of an MRA have been developed and proposed by Virage Logic [11,12], National Tsing Hua University [13,14,15,16,17], and others [4,19,20,21,22]. One of the main drawbacks of the proposed approaches is that, to reduce the simulation complexity, they limit realistic faults into memory devices, and do not enable the MRA evaluation under an elevated number of di↵erent faulty memory configurations.…”

Section: Introductionmentioning

confidence: 99%

SIERRA—Simulation environment for memory redundancy algorithms

Scionti

Mazumdar

Carlo

et al. 2016

Simulation Modelling Practice and Theory

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Section: Introductionmentioning

confidence: 99%

SIERRA—Simulation environment for memory redundancy algorithms

Scionti

Mazumdar

Carlo

et al. 2016

Simulation Modelling Practice and Theory

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“…Alternatively, we may assume that it is reconstructed at each power up time by scanning memory reflecting the changing memory status. Fig 3 shows the overhead of using defect map compared with the existing redundancy approach in [4] and [5] for 100% embedded SRAM yield. Note that the Y-axis in Fig 2 is a log scale.…”

Section: Introductionmentioning

confidence: 99%

“…The redundancy scheme in [4] can at most repair only 0.003% defects thus the data used for that level of defects is based on approach in [4]. For higher defect rates we used the data from [5]. The defect map can be implemented in one of two ways: (1) using CAM (Content-Addressable Memory) and (2) using a tag bit for every data word (TAG).…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs

Jung

Cheng

et al. 2006

Advances in Computer Systems Architecture

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Abstract. In the foreseeable future, System-on-Chip design will suffer from the problem of low yield especially in embedded memories. This can be a critical problem in a multimedia application like H.264 since it needs a huge amount of embedded memory. Existing approaches to solve this problem are not feasible given the higher memory defect density rates in technologies below 90 nm. In this paper, we present a new defect-resilience technique which employs the directional image filter in order to recover data from corrupted embedded memory. According to the analysis based on simulation the proposed filter can greatly improve the visual quality of the defected H.264 video streams with errors in data memory reaching up to 1.0% memory BER (Bit Error Rate) with lower power consumption relative to conventional median filter. Therefore, the proposed method can be a good solution to overcome the problem of low yield in multimedia SoC memory without suffering from additional redundant memory overhead.

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Memory Defect Tolerance Architectures for Nanotechnologies

Nicolaidis¹,

Anghel

Achouri³

2005

J Electron Test

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Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing in future submicron technologies, more advanced solutions may be required for memories to be produced in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels of several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents several Built-In Self Repair techniques addressing memories affected by high defect densities as well as an evaluation of the area cost and yield. Statistical fault injection simulations were conducted and the obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories

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Evaluation of memory built-in self repair techniques for high defect density technologies

Cited by 5 publications

References 15 publications

SIERRA—Simulation environment for memory redundancy algorithms

SIERRA—Simulation environment for memory redundancy algorithms

Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs

Memory Defect Tolerance Architectures for Nanotechnologies

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