Evaluation of Hot Carrier Impact on Lateral-DMOS with LOCOS feature

Abstract

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH, ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were found to be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flicker noise assessment under the same stress shows noticeable instabilities.

Design of an LDMOS Transistor Based on the 1 µm CMOS Process for High/Low Power Applications

“…Next, we examined the transistor gain as a function of frequency for multiple gate voltages, using Mason's unilateral gain (MUG) Figure 5 shows the 2D scalar distribution of the absolute value of the electric field and with its extracted maximum path. The bird's beak and near areas have the highest values, and we reported that it triggers noticeable degradation under hot carrier injection [17,18]. As mentioned earlier, the LDMOS operates in RF modes, thus it is important to determine its frequency response.…”

“…Figure 5 shows the 2D scalar distribution of the absolute value of the electric field and with its extracted maximum path. The bird's beak and near areas have the highest values, and we reported that it triggers noticeable degradation under hot carrier injection [17,18]. Figure 3c shows the output characteristic plotted for various V GS values.…”