Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

Stroud, Charles E.; Chen, Ping; Konala, S.; Abramovici, M.

doi:10.1109/fpga.1996.242437

Cited by 55 publications

(19 citation statements)

References 2 publications

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“…Testing before programming presents a wide spectrum of problems, for which a number of researchers have proposed innovative solutions. [3][4][5][6][7][8] Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations (programmings) of the FPGA.…”

mentioning

confidence: 99%

Testing the interconnect of RAM-based FPGAs

Renovell

Portal

Figueras

et al. 1998

IEEE Des. Test. Comput.

131

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PROGRAMMABLE LOGIC in the form of field-programmable gate arrays has become a widely accepted design approach for lowand medium-volume computing applications. Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology. FPGAs are regular structures of logic modules communicating via an interconnect architecture of lines and switches. Users program the logic modules and interconnect structures to perform particular functions and realize the FPGA's global function. 1,2 Manufacturers provide programmability in their FPGA architectures in various ways. They may use RAM to store configuration information, EPROM switches based on FAMOS (floating-gate avalanche-injection metal oxide semiconductor) transistors and fuses, or antifuses that permanently open or close connections. Of these alternatives, we have focused our work on RAM-based FPGAs. Their simplicity and flexibility for user changes in the field make this type of FPGA a very popular choice among designers.The architecture and design of these devices have been widely investigated during the last decade, but their test challenges have received less attention. Only recently have researchers addressed the problem of testing after manufacture-in other words, before user programming of specific functions. Testing before programming presents a wide spectrum of problems, for which a number of researchers have proposed innovative solutions. [3][4][5][6][7][8] Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations (programmings) of the FPGA. But changing configurations incurs reprogramming costs. So the question arises: How can we determine the minimum number of test configurations and corresponding vector test sequences that will cover all the faults of an FPGA's structural fault model?Dealing with this question in an earlier work, we proposed a general methodology for test configuration and test pattern generation. 5 Here, we apply this methodology to the interconnect structure. We propose a manufacturing test procedure for RAMbased FPGA interconnect structures. FPGA testing methodologyOur FPGA testing approach distinguishes two types of inputs: operation and configuration. One uses operation inputs during normal circuit operation to apply input vectors IV 1 … IV n . One usually uses configuration inputs before normal circuit operation to configure the FPGA. A given FPGA configuration consists of a long bit stream, entered block by block into the circuit. These blocks can be

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mentioning

confidence: 99%

Testing the interconnect of RAM-based FPGAs

Renovell

Portal

Figueras

et al. 1998

IEEE Des. Test. Comput.

131

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“…The approach of [3] utilizes a BET-based technique, in which the logic resources are configured as units under test, test generators and verifiers. [9] has presented a new approach for testing FPGAs by utilizing their programmable and reconfiguration capabilities.…”

Section: : Reviewmentioning

confidence: 99%

“…An area which only recently has been investigated, is testing and diagnosis. For logic resources, two approaches can be distinguished: the B E T (Built-In Self-Test)-based approach of [3] and the array-based approach of [4,9]. However, both these approaches are applicable t o FPGAs and to logic resource testing only; it has been reported that in a VLSI chip of this nature, the most likely place for a fault is the interconnect [6,10].…”

Section: : Introductionmentioning

confidence: 99%

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Testing of programmable logic devices (PLD) with faulty resources

Ashen

Meyer²,

Park³

et al.

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such a s built-in self-test schemes (for ezample, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines. 1: IntroductionIn the last few years, research in programmable chips such as field programmable gate arrays (FPGAs) has experienced a tremendous growth [lo]. An area which only recently has been investigated, is testing and diagnosis. For logic resources, two approaches can be distinguished: the B E T (Built-In Self-Test)-based approach of [3] and the array-based approach of [4,9]. However, both these approaches are applicable t o FPGAs and to logic resource testing only; it has been reported that in a VLSI chip of this nature, the most likely place for a fault is the interconnect [6,10]. An extensive literature exists for interconnect testing and diagnosis [1,2]. However, the issue of testing a programmable chip and its interconnect (complete testing) has not been addressed. A family of logic devices which has not been analyzed in depth is the so-called PLD (programmable logic device) [8] A PLD consists of sophisticated routing resources which connect very simple logic resources (usually the basic cell is made of a LUT with few input variables and a sequential element).The objective of this paper is to propose a methodology for complete PLD testing (both logic and interconnect resources); this methodology exploits BIST and array-based arrangements (such as proposed in [3,9] for testing logic resources) combined with a walking test set for multiple fault detection in the interconnect channels and lines. 2: ReviewTesting of logic resources in FPGAs has been dealt using two different approaches. The approach of [3] utilizes a BET-based technique, in which the logic resources are configured as units under test, test generators and verifiers.[9] has presented a new approach for testing FPGAs by utilizing their programmable and reconfiguration capabilities.For faults in the interconnect it is commonly postulated that every net can be shorted to any other net [1,2]. The Counting Sequence Algorithm of [2] can be used to detect all bridge faults with a test length of log, n where n is the number of nets. The walking test set proposed by [l] (walking-1) can be used to diagnose all bridge, stuck-at and open faults in the nets; the test set is a sequence '

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“…Field Programmable Gate Arrays (FPGAs) combine the flexibility of mask programmable gate arrays with the convenience of field programmability [1][2][3][4][5][6][7][8][9][10][11][12]. There are many FPGA types but one very important is the static-RAM based FPGA architecture.…”

Section: Introductionmentioning

confidence: 99%

Analyzing the test generation problem for an application-oriented test of FPGAs

Renovell

Portal²,

Faure³

et al.

Proceedings IEEE European Test Workshop

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renovell@ lirinm.fr figueras@eel.upc.es zorian @lvision.com 34392 Montpellier France Barcelona Spain San Jose CA 951 10 USA Tel(33)46 741 8.523 Tel(34)34016603 Tel(1)4084S30146 AbstractThe objective of this paper is to generate a ApplicationOriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non- redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattem generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattem generation petformed on a FPGArepresentation is required. it is then demonstrated that test pattem generation performed on the FPGA representation can be significantly accelerated by removing' most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.

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Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

Cited by 55 publications

References 2 publications

Testing the interconnect of RAM-based FPGAs

Testing the interconnect of RAM-based FPGAs

Testing of programmable logic devices (PLD) with faulty resources

Analyzing the test generation problem for an application-oriented test of FPGAs

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