Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations

Yabuuchi, Michitarou; Kobayashi, Kazutoshi

doi:10.1109/fpt.2010.5681449

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…BTI-induced degradations on ASICs are discussed in [4]- [7]. BTI-induced degradations on FPGAs are discussed in [8]- [11]. Conventionally, the correlation among BTI-induced degradations and process variations are not discussed.…”

Section: Introductionmentioning

confidence: 99%

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

Yabuuchi

Kishida

Kobayashi

2014

IEICE Trans. Fundamentals

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We analyze the correlation between BTI (Bias Temperature Instability)-induced degradations and process variations. Those reliability issues are correlated. BTI is one of the most significant agingdegradations on LSIs. Threshold voltages of MOSFETs increase with time when biases stress their gates. It shows a strong effect of BTI on highly scaled LSIs in the same way as the process variations. The accurate prediction of the combinational effects is indispensable. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure frequencies of ROs (Ring Oscillators) of 65-nm process test circuits on two types of LSIs, ASICs and FPGAs. There are 98 and 837 ROs on our ASICs and FPGAs respectively. The frequencies of ROs follow gaussian distributions. We describe the highest frequency group as the "fast" conditon, the average group as the "typical" conditon and the lowest group as the "slow" conditon. We measure the aging-degradations of the ROs of the three conditions on the accelerated test. The degradations can be approximated by logarithmic function of stress time. The degradation at the "fast" condition has a higher impact on the frequency than the "slow" one. The correlation coefficient is 0.338. In this case, we can define a smaller design margin for BTI-induced degradations than that without considering the correlation because the degradation at the "slow" conditon is smaller than the average and the fast.

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Section: Introductionmentioning

confidence: 99%

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

Yabuuchi

Kishida

Kobayashi

2014

IEICE Trans. Fundamentals

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“…The rising delays and the falling delays are changed by the degradation and depend on the circuit conditions. Performance of FPGAs is degraded by the degradation effects [3]. We propose two design methodologies to compensate NBTI degradation by optimizing the condition of routing structures of FPGAs.…”

Section: Introductionmentioning

confidence: 99%

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Yabuuchi

Kobayashi

2012

IPSJ Transactions on System LSI Design Methodology

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Abstract:Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.

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A Scalable and Process Variation Aware NVM-FPGA Placement Algorithm

Yang

Xue

2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations

Cited by 3 publications

References 15 publications

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

A Scalable and Process Variation Aware NVM-FPGA Placement Algorithm

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