Evaluation of final test process in 64-Mbit DRAM manufacturing system through simulation analysis

Abstract

We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an eventdriven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMs and SDRAMs are considered. The overall number of planned production chips during a month is 3 millions. The number ofchips simultaneously tested is 32,64, 128, and 256. Simulations for six months were canied out as a function of number of memory test system:. by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.

A framework for standard modular simulation :

“…al. in [43] reported how simulation was utilized to optimize the testing process for VLSI circuits: Dynamic Random Access Memories (RAMs), and Synchronous Dynamic Access Memories (DRAMs). The objective was to obtain the optimal number of testers according to the best trade-off between Turn Around Time (TAT) and cost per chip.…”

Framework for Fault Analysis and Test Generation in DRAMs

“…The memory test flow is a description of the stages and activities needed to test memory devices. Figure 1 shows a block diagram of a typical manufacturing test flow for a memory manufacturer [Nakamae03]. The figure also shows a three-stage representation of the design flow, starting with the specification of a new memory technology, followed by the design process and ending with chip manufacturing.…”

“…The process of DRAM testing has developed into a rather complex combination of historically proven test sets, highly specialized expert knowledge, and cuttingedge failure analysis (FA) methods to evaluate any newly encountered failure mechanisms [Nakamae03]. However, many of these test development methods follow two main paths, 1. test development based on memory specifications, and 2. test development based on post-manufacture failure analysis.…”