Evaluation of different Rijndael implementations for high end servers

Mayer, U.; Oelsner, C.; Köhler, Tim

doi:10.1109/iscas.2002.1010996

Cited by 11 publications

(12 citation statements)

References 4 publications

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“…Since our primary concern was latency performance, we opted for the fastest direct implementation. Using the same constraint considerations, a similar conclusion can also be reached using figures from other authors [6].…”

Section: S-box Designsupporting

confidence: 75%

Design and performance testing of a 2.29-GB/s rijndael processor

Verbauwhede

Schaumont

Kuo

2003

IEEE J. Solid-State Circuits

176

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Abstract-This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-m CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.

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Section: S-box Designsupporting

confidence: 75%

Design and performance testing of a 2.29-GB/s rijndael processor

Verbauwhede

Schaumont

Kuo

2003

IEEE J. Solid-State Circuits

176

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“…The hardware implementation of crypto algorithms, associated with keys, is by nature very secure and cannot be easily modified from outside [3]. After the Rijndael algorithm has become a standard encryption algorithm, many hardware implementations based on FPGA and ASIC have been proposed [3][4][5][6][7][8][9]. ASIC provides low power design but the design time and time to market is very high.…”

Section: Introductionmentioning

confidence: 99%

FPGA implementation of AES-based crypto processor

Anwar

Daneshtalab

Ebrahimi

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.

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“…Various methods for constructing compact inversion circuits over GF have been studied, based on Fermat's Little Theorem, the extended Euclid's Algorithm and so on [11]. In particular, the composite field (or tower field) inversion [8] is effective over GF (2 8 ), and it can be used to create compact AES implementations [9,10].…”

Section: Basic Approachesmentioning

confidence: 99%

“…[13], or by making a decision diagram such as a BDD [12] or an FDD [14]. In many actual AES implementations the table-lookup method is used [11], where the S -Box circuit is automatically synthesized using EDA tools.…”

Section: Basic Approachesmentioning

confidence: 99%

See 1 more Smart Citation

A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

Morioka

Satoh

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

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In this paper, we present a high-speed AES IP-core, which runs at 780 MHz on a 0.13µm CMOS standard cell library, and which achieves 10 Gbps throughput in all encryption modes, including CBC mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining techniques cannot be applied. To reduce the propagation delays of the S -Box, the most critical function block, we developed a special circuit architecture that we call twisted-BDD, where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S -Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.

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Evaluation of different Rijndael implementations for high end servers

Cited by 11 publications

References 4 publications

Design and performance testing of a 2.29-GB/s rijndael processor

Design and performance testing of a 2.29-GB/s rijndael processor

FPGA implementation of AES-based crypto processor

A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

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