A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

Morioka, Sumio; Satoh, Akashi

doi:10.1109/iccd.2002.1106754

Cited by 52 publications

(23 citation statements)

References 10 publications

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“…As far as we know, this is the fastest nonpipelined AES encryption rate implemented in actual silicon. (Other work [11], however, based on simulations using 0.13m CMOS has shown a faster AES core.) The WDDL AES was able to operate at a maximum of 85.5 MHz, which is equivalent to 0.99 Gb/s.…”

Section: B Ic Performance Resultsmentioning

confidence: 99%

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Hwang¹,

Tiri²,

Hodjat

et al. 2006

IEEE J. Solid-State Circuits

137

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Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-m CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.

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Section: B Ic Performance Resultsmentioning

confidence: 99%

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Hwang¹,

Tiri²,

Hodjat

et al. 2006

IEEE J. Solid-State Circuits

137

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“…S. Morioka et al optimized throughput [9] using the optimization of S-Box for the AES algorithm. He also optimized S-Box to minimize consumption of power [10]; in addition, he tried to reduce area consumption for S-Box implementation [11].…”

Section: Related Workmentioning

confidence: 99%

Single Event Effects Tolerant AES-CTR Implementation for Authentication of Satellite Communication

Pirzada¹,

Murtaza²,

Liu³

et al. 2019

IJCCE

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Recently, the increase in the use of fast and reliable communication systems has increased the significance and utilization of satellite-based communication systems. The communication systems used in the space environment is more reliable and robust as compared to communication systems used on earth. Because unlike ground communication, the communication systems in space have to bear harsh space environment and its effects like radiations, pressure, and vacuum, which causes anomalies in communication systems. These effects are known as Single Event Effects (SEE), which results in loss of data or sometimes even damage to the equipment. Like ground systems, in satellite, the Advanced Encryption Standard (AES) is a widely used encryption algorithm which is not only used to provide data confidentiality but also used in data authentication & integrity algorithms (e.g. CMAC) as well as in authenticated encryption (AE) algorithm (e.g., AES-GCM). The Substitution Box (S-Box) is a main component of the AES algorithm, which is generally implemented on memory blocks. The memory blocks in space are vulnerable to radiations and mostly affected by SEE; hence, protection techniques against SEE are proposed by researchers. Two methods for implementation of the S-Box algorithm are by a look-up table or by an algorithm. In this work, analysis of using these two methods of the S-Box implementation for SEE is performed. The implementation of both methods is performed on FPGA, and results show that the algorithm implementation is more reliable in the space environment as compared to table-based implementation.

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“…The common technique used to enhance the performance of AES system is by using pipelining, which acquired a throughput of 8 Gbps [2]. The first AES implementation with a throughput over 10 Gbps was proposed by applying T-box, which is a combination of the Sub Bytes, Shift Rows, and Mix Columns phases in the AES algorithm [3]. A fully pipelined AES processor has more complex operations and achieves throughput between 30 and 70 Gbps [4].…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of efficient AES encryption

Priya

Kumar

Sivamangai

et al. 2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5.Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.

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A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

Cited by 52 publications

References 10 publications

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Single Event Effects Tolerant AES-CTR Implementation for Authentication of Satellite Communication

FPGA implementation of efficient AES encryption

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A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

Cited by 52 publications

References 10 publications

AES-Based Security Coprocessor IC in 0.18-&lt;tex&gt;$muhbox m$&lt;/tex&gt;CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

AES-Based Security Coprocessor IC in 0.18-&lt;tex&gt;$muhbox m$&lt;/tex&gt;CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Single Event Effects Tolerant AES-CTR Implementation for Authentication of Satellite Communication

FPGA implementation of efficient AES encryption

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AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks