Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes

Abstract

The charge build-up evaluation technique in semiconductor wafer processing such as ion implantation and plasma processing by using the MOS capacitor with charge collecting electrode (antenna) has been proposed. The estimation of charge build-up during ion implantation has been successfully demonstrated by using this technique. The charge detection sensitivity of a small area MOS capacitor can be improved by using the antenna structure. To estimate charge build-up quantitatively, gate oxide thickness, substrate type, capacitor area and antenna ratio should be carefully chosen. This technique is very useful to estimate charge build-up in conjunction with other charge build-up detection technique such as EEPROM.

Control of Plasma Damage to Gate Oxide during High Density Plasma Chemical Vapor Deposition

“…Antenna structures, where a large conductor over field oxide is connected to a small transistor over thin gate oxide, have been shown to be useful for detecting this charging damage. 4 In this study, gate oxide damage resulting from PECVD and HDP CVD oxide deposition was investigated by using gate leakage of transistors connected to metal antenna structures with area ratios from 6,000:1 up to 200,000:1. Only slight gate oxide damage was detected from the PECVD oxide deposition, but significant damage was detected from an unoptimized HDP CVD oxide deposition process.…”