2018
DOI: 10.1088/2053-1583/aab728
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Evaluation of border traps and interface traps in HfO 2 /MoS 2 gate stacks by capacitance–voltage analysis

Abstract: Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent C–V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices. The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states… Show more

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Cited by 78 publications
(69 citation statements)
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References 32 publications
(48 reference statements)
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“…On the other hand, the top high‐ k oxide is typically formed on the inert MoS 2 surface by atomic layer deposition (ALD) at a relatively low temperature with the aid of a buffer layer, which may introduce many traps inside. The traps close to the interface serve as quick traps while the traps inside the oxide serve as slow traps, as discussed in several reports . Third, trap (III) represents the strain in MoS 2 induced externally.…”
Section: Introductionmentioning
confidence: 94%
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“…On the other hand, the top high‐ k oxide is typically formed on the inert MoS 2 surface by atomic layer deposition (ALD) at a relatively low temperature with the aid of a buffer layer, which may introduce many traps inside. The traps close to the interface serve as quick traps while the traps inside the oxide serve as slow traps, as discussed in several reports . Third, trap (III) represents the strain in MoS 2 induced externally.…”
Section: Introductionmentioning
confidence: 94%
“…Here, the recent demonstration of a natural thin‐body MoS 2 FET with an effective channel length of ≈ 3.9 nm has facilitated research on 2D layered channels due to overcoming the scaling limit of ≈ 5 nm for Si gate length . Although the dangling‐bond‐free surface of the layered channel is expected to ideally provide an electrically inert interface, there are many reports on the wide range of interface state densities ( D it ) from 10 11 to 10 13 eV −1 cm −2 for high‐ k top‐gate n ‐MoS 2 FET in reality, which must be reduced to improve the device performance. To date, several physical origins for D it have been proposed, which are summarized in Figure a.…”
Section: Introductionmentioning
confidence: 99%
“…[77][78][79][80][81][82][83][84][85] By exploiting the O 3 surface functionalization approach for high-j dielectric ALD, Zhao et al demonstrated the ability to employ electrical characterization test structures incorporating a more conventional top gate geometry, thereby enabling an inroad to understanding the impact of defects at the high-j/MoS 2 interface as well as those associated with the high-j itself through impedance spectroscopy. 77,80,84 Figure 10 presents the transistor test structure schematic and the associated TEM cross section of a top gate device stack achieved after HfO 2 ALD enabled by O 3 -functionalization. It is seen that the physical characterization reveals a uniform HfO 2 deposition on the 7-layer exfoliated and transferred MoS 2 layer on SiO 2 .…”
Section: Device Characterization Of Uv-ozone Functionalized Mosmentioning
confidence: 99%
“…The impact of annealing in N 2 and forming gas (N 2 :H 2 ) has also been studied to better optimize the device response, 82 as well as the detailed extraction methods for interface defect traps and nearby (border) defect traps in the HfO 2 using these structures. 84 The details of the device test structure and the electrical characterization and property extraction (e.g., D it ) remain a contemporary research topic in the community. Interface state density for HfO 2 /MoS 2 / SiO 2 /Si on the order of 10 13 /cm 2 eV as well as the presence of significant border traps in the high-j dielectric has been reported.…”
Section: Device Characterization Of Uv-ozone Functionalized Mosmentioning
confidence: 99%
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