Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links

Quesada-Martinez, Andres; Aparicio-Morales, Javier; Campos-Araya, Jose; Chacón-Rodríguez, Alfonso; García-Ramírez, Ronny; Rimolo-Donadío, Renato

doi:10.1109/lascas45839.2020.9069001

Cited by 3 publications

(5 citation statements)

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“…The designs which use BRAM have an increased dynamic power draw. The dynamic power draw of the encoders from [28] is ten times higher than the rest of the encoders, which might be due to the different tool versions (unspecified in [28]).…”

Section: Resultsmentioning

confidence: 99%

“…We successfully simulated, synthesized, and implemented these codecs in Vivado 2023.1 and included them in the comparisons. In [28], we found the only 8b/10b encoder FPGA implementations from the literature that were well-documented in terms of resource utilization, power draw, and maximum operating frequency or longest propagation time. These implementations targeted the AMD Kintex-7 KC705 evaluation board [13] with the XC7K325T-2FFG900C FPGA device, and have a similar interface and functionality to our encoders.…”

Section: Resultsmentioning

confidence: 99%

“…We constrained our designs to be paced by a 250 MHz clock signal with a 100 ps input jitter. The same clock frequency as in [28] was used for Impl. 1 and Impl.…”

Section: Resultsmentioning

confidence: 99%

“…2. For the power draw comparisons, we used the same default tool parameters as in [28]: no output load (i.e., 0 pF), typical process, nominal power supply voltages, an input toggle rate of 12.5%, and a static probability of 50%, along with the same 250 MHz clock signal and a 25 • C environment temperature. For all the decoders, we estimated the power draw using the SAIF files resulting from the verification simulations.…”

Section: Resultsmentioning

confidence: 99%

“…1 and Impl. 2 from [28] to the Aurora 8B/10B core in terms of power consumption, propagation delay, and resource utilization.…”

Section: Discussionmentioning

confidence: 99%

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Optimal Implementations of 8b/10b Encoders and Decoders for AMD FPGAs

Popa,

Ivanovici,

Coliban

2024

Electronics

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The 8b/10b IBM encoding scheme is used in a plethora of communication technologies, including USB, Gigabit Ethernet, and Serial ATA. We propose two primitive-based structural designs of an 8b/10b encoder and two of an 8b/10b decoder, all targeted at modern AMD FPGA architectures. Our aim is to reduce the amount of resources used for the implementations. We compare our designs with implementations resulting from behavioral models as well as with state-of-the-art solutions from the literature. The implementation results show that our solutions provide the lowest resource utilization with comparable maximum operating frequency and power consumption. The proposed structural designs are suitable for resource-constrained data communication protocol implementations that employ the IBM 8b/10b encoding scheme. This paper is an extended version of our paper published at the 2022 International Symposium on Electronics and Telecommunications (ISETC), Timisoara, Romania, 10–11 November 2022.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…We constrained our designs to be paced by a 250 MHz clock signal with a 100 ps input jitter. The same clock frequency as in [28] was used for Impl. 1 and Impl.…”

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…1 and Impl. 2 from [28] to the Aurora 8B/10B core in terms of power consumption, propagation delay, and resource utilization.…”

Section: Discussionmentioning

confidence: 99%

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