An Optimal Implementation of an 8b/10b Encoder for Xilinx FPGAs

Optimal Implementations of 8b/10b Encoders and Decoders for AMD FPGAs

“…In contrast with the results presented in [16], the optimized Beh. 1 encoder implementation obtains slightly worse results relative to the golden model.…”

“…For simulation, synthesis, and implementation on AMD FPGAs, we used the AMD Vivado Design Suite version 2023.1. Our previous work regarding an LUT-based 8b/10b encoder similar to the one presented in Section 2.2.2, presented in [16], was achieved using version 2022.1 of the same tool.…”

“…The general view of the proposed 8b/10b encoder architecture is presented in Figure 5, with emphasis on the signal dependencies between the 5b/6b and 3b/4b encoding schemes. A similar architecture was detailed in [16], although without the cascading functionality. The Boolean equations of all signals except the encoding schemes are detailed in Appendix A.…”

“…The optional error block raises the error signal for input byte values that do not correspond to any special symbol if the k_i input signal is high. D.x.A7 is used instead of D.x.P7 for x ∈ {11, 13, 14}, when rd_i = 0 x ∈ {17, 18, 20}, when rd_i = 1 (4) Modified from [16].…”

“…The proposed LUT-based AMD FPGAs-specific 8b/10b encoder organization is detailed in Figure 7. A similar design was briefly presented in [16], though without the cascading functionality and the LUTs configuration. The logic/Boolean functions implemented by the LUTs are listed in Table 5 as little-endian truth table values expressed in hexadecimal.…”