Evaluating SEU fault-injection on parallel applications implemented on multicore processors

Vargas, Vanessa; Ramos, Pablo; Velazco, Raoul; Méhaut, Jean‐François; Zergainoh, Nacer-Eddine

doi:10.1109/lascas.2015.7250449

Cited by 11 publications

(5 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The validation of the proposed approach was done by SWIFI, which is a useful technique to emulate SEU effects. The adopted approach was proven in our previous works concerning fault-injection for multi-core processors [7,[37][38][39]. It is important to note that the objective of this approach is to reproduce the SEUs effects, which are bit-flips in memory cells caused by natural radiation.…”

Section: Resultsmentioning

confidence: 99%

“…The fault-injection technique proposed in this approach to emulate SEU is an SWIFI technique. As was previously stated, the approach validated in our previous works concerning fault-injection on multi-core processors [7,[37][38][39] is based on Code Emulated Upset (CEU) principles [47], which reproduce, without intrusion, the effects of SEUs. This is achieved by the assertion of asynchronous interrupt signals.…”

Section: Fault-injection Detailsmentioning

confidence: 99%

See 1 more Smart Citation

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

Self Cite

View full text Add to dashboard Cite

The N-Modular Redundancy and M-Partitions (NMR-MPar) fault-tolerance approach can be used to improve the reliability of embedded systems that are based on Commercial-Off-The-Shelf (COTS) multi-/many-core processors, especially those with a non-critical time constraint allowing a diminution in performance to gain reliability by maintaining power consumption. Typically, mixed-criticality systems, such as avionics or spacecraft, comply with these requirements.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Fault-injection Detailsmentioning

confidence: 99%

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, the circuit can be restored to its original working state by rewriting or resetting. Hence SEUs constitute reversible soft errors [100].…”

Section: Single Event Upsetsmentioning

confidence: 99%

On the Security of LEO Satellite Communication Systems: Vulnerabilities, Countermeasures, and Future Trends

Yue¹,

An²,

Zhang³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…By using the fork() and ptrace() system calls and operating system signals (e.g., SIGSTOP and SIGCONT) Vargas et al [91] develop a faultinjection tool that is hardware-independent (but not operating system-independent) and can inject faults into general purpose registers, some selected special purpose registers and in memory regions. The parent process (after the fork() call) is used as the fault injector and the child process executes the…”

Section: Hardware Fault Injectionmentioning

confidence: 99%

“…Software-based fault injection [50,91,98] affects the execution time and thus it may be hard to verify WCET estimates in presence of faults.…”

Section: (Question 1 and 2)mentioning

confidence: 99%

Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

View full text Add to dashboard Cite

With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

show abstract

Evaluating SEU fault-injection on parallel applications implemented on multicore processors

Cited by 11 publications

References 13 publications

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

On the Security of LEO Satellite Communication Systems: Vulnerabilities, Countermeasures, and Future Trends

Timing Predictability in Future Multi-Core Avionics Systems

Contact Info

Product

Resources

About