Evaluating on-chip interconnects for low operating frequency silicon neuron arrays

Cassidy, Andrew; Murray, Thomas G.; Andreou, Andreas G.; Georgiou, Julius

doi:10.1109/iscas.2011.5938096

Cited by 6 publications

(3 citation statements)

References 14 publications

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“…In contrast, BrainScaleS utilizes an isynchronous inter-chip communication network, which means that events occur regularly [2369], [2370]. AER communication has also been utilized for on-chip communication [2371], [2372], but it has been noted that there are limits of AER for on-chip communication [2373]. As such, there are several other approaches that have been used to optimize intra-chip communication.…”

Section: A Communicationmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

172

180

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Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brainlike ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

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Section: A Communicationmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

172

180

View full text Add to dashboard Cite

show abstract

“…Since every single event produced by any neuron has to travel through the single AER bus and Mapper, the system's maximum total event traffic is limited by the bus bandwidth. If N tot is the total number of neurons, f n is the mean spike rate per neuron and F out the average fan-out per neuron (spike repetitions introduced by the mapper to emulate the projection fields and/or synaptic weighting), the event arrival rate λ at the Mapper output channel is [34] λ = N tot f n F out . If E f lat is the physical channel bandwidth, then the channel service rate is µ = E f lat and the average time an event waits to be serviced is (assuming an M/M/1 queue model [35])t q = 1/ (µ − λ).…”

Section: Review Of Aer Approaches For Large Scale Systemsmentioning

confidence: 99%

Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets

Zamarreno-Ramos

Linares-Barranco

Serrano-Gotarredona

et al. 2013

IEEE Trans. Biomed. Circuits Syst.

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This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64 × 64 pixels with kernels with sizes up to 11 × 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 × 10(3) neurons and almost 32 million synapses.

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“…By combining novel knowledge from neuroscience, researchers in neuromorphic engineering aim to build electronic systems that have the efficiency of biological computation [7,8]. Recent years have witnessed increasing efforts in event-based neuromorphic systems [9][10][11][12][13][14][15][16]. The aim is to emulate biological use of asynchronous, sparse, event-driven signaling as a core aspect of its computational architecture.…”

Section: Event-based Processing and Neuromorphic Systemsmentioning

confidence: 99%

A biologically inspired human posture recognition system

Bo¹

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Evaluating on-chip interconnects for low operating frequency silicon neuron arrays

Cited by 6 publications

References 14 publications

A Survey of Neuromorphic Computing and Neural Networks in Hardware

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets

A biologically inspired human posture recognition system

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