Estimating switching losses for SiC MOSFETs with non-flat miller plateau region

Agrawal, Bharat; Freindl, Matthias; Bilgin, Berker; Emadi, Ali

doi:10.1109/apec.2017.7931075

Cited by 38 publications

(7 citation statements)

References 10 publications

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“…The last two of the mentioned cases could be achieved for low R g and/or a low transistor turn-off current I L . Moreover, for the second and third instances, the turn-off loss is reduced [11,16,21]. The described cases are depicted in Figure 2a-c.…”

Section: Sic Mosfet Zero Turn-off Loss Process Phenomenamentioning

confidence: 97%

Experimental Investigation on SiC MOSFET Turn-Off Power Loss Reduction Using the Current Sink Capacitor Technique

Harasimczuk,

Kopacz,

Trochimiuk

et al. 2023

Energies

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This paper investigates the current sink capacitor technique as a method to minimize the turn-off power losses of SiC MOSFETs operated with zero-voltage switching (ZVS). The method is simple and is based on adding auxiliary capacitors in parallel to the transistors, allowing the sink capacitor to take over part of the channel current, thus limiting the power loss while also advantageously lowering the dvds/dt ratio. The technique is validated and experimentally studied based on a single-pulse test setup with 1200 V-rated SiC MOSFETs, with several capacitances and gate resistance values, at various switched currents up to roughly 60 A. It is shown that by employing even very small capacitances, in the range of nanofarads, the turn-off power loss can be reduced by over tenfold, with a negligible impact on the volume and complexity of the system. Thus, the presented method can be effectively employed to improve soft-switched power converters.

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Section: Sic Mosfet Zero Turn-off Loss Process Phenomenamentioning

confidence: 97%

Experimental Investigation on SiC MOSFET Turn-Off Power Loss Reduction Using the Current Sink Capacitor Technique

Harasimczuk,

Kopacz,

Trochimiuk

et al. 2023

Energies

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“…Hence, the switching losses are independent on the switched power current (I load ), and only depend on the converter input voltage, the switching frequency, and the device parasitic capacitance as presented in equations ( 3) and (4). Knowing the device architecture and the gate charge waveforms, which is not the case for diamond based devices, the model could be further improved to account for both the turn-off loss and the load current dependence on the switching loss, as proposed in [41].…”

Section: R Onmentioning

confidence: 99%

Analytic modeling of a hybrid power module based on diamond and SiC devices

Couret

Castelan

Donato

et al. 2022

Diamond and Related Materials

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“…Transistor switching power losses can be determined based on waveforms of the transistor drain-source voltage and the drain current collected during a double-pulse test. The doublepulse test is a well-known and widely acknowledged method of determining switching power losses in transistors [27][28][29][30]. A simplified schematic of the double-pulse test testbench has been shown in Fig.…”

Section: Power Losses In Mosfet Transistorsmentioning

confidence: 99%

Bulletin of the Polish Academy of Sciences: Technical Sciences

Zięba,

Rąbkowski

2022

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High-speed switching capabilities of SiC MOSFET power modules allow building high power converters working with elevated switching frequencies offering high efficiencies and high power densities. As the switching processes get increasingly rapid, the parasitic capacitances and inductances appearing in SiC MOSFET power modules affect switching transients more and more significantly. Even relatively small parasitic capacitances can cause a significant capacitive current flow through the SiC MOSFET power module. As the capacitive current component in the drain current during the turn-off process is significant, a commonly used method of determining the switching power losses based on the product of instantaneous values of drain-source voltage and drain current may lead to a severe error. Another problem is that charged parasitic capacitances discharge through the MOSFET resistive channel during the turn-on process. As this happens in the internal structure, that current is not visible on the MOSFET terminals. Fast switching processes are challenging to measure accurately due to the imperfections of measurement probes, like their output signals delay mismatch. This paper describes various problems connected with the correct determination of switching power losses in high-speed SiC MOSFET power modules and proposes solutions to these problems. A method of achieving a correct time alignment of waveforms collected by voltage and current probes has been shown and verified experimentally. In order to estimate SiC MOSFET channel current during the fast turn-off process, a method based on the estimation of nonlinear parasitic capacitances current has also been proposed and verified experimentally.

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Estimating switching losses for SiC MOSFETs with non-flat miller plateau region

Cited by 38 publications

References 10 publications

Experimental Investigation on SiC MOSFET Turn-Off Power Loss Reduction Using the Current Sink Capacitor Technique

Experimental Investigation on SiC MOSFET Turn-Off Power Loss Reduction Using the Current Sink Capacitor Technique

Analytic modeling of a hybrid power module based on diamond and SiC devices

Bulletin of the Polish Academy of Sciences: Technical Sciences

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