Estimating error rates in processor-based architectures

Abstract

The paper investigates a new technique to predict error rates in digital architectures based on microprocessors. Three studied cases are presented concerning three different processors. Two of them are included in the instruments of a satellite project. The actual space applications of these two instruments were implemented using the capabilities of a dedicated system. Results of the fault injection and radiation testing experiments and discussions about the potentialities of this technique are presente

Optimization of a self-converging algorithm at assembly level to improve SEU fault-tolerance

“…To emulate the occurrence of SEUs during the execution of the self-converging algorithm we used the CEU approach [6]. As stated before, this approach, devoted to fault injection in processor-like devices, is based in the assertion at a randomly chosen clock cycle, of an asynchronous signal, such as an interrupt.…”

“…Among targeted resources can be mentioned general-purpose registers, special function registers, internal SRAM, memory caches, etc. Results of the application of the CEU approach to representative circuits (processors, FPGAs) can be found in [6][7][8].…”

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

“…The second step is to determine the probability that a SEU cause a system error. It has been shown [10][11][12][13][14] that this probability is related with the application cross section, denoted by AP . To increase system reliability, the application cross section should be reduced by means of fault tolerant techniques.…”

Impact of data cache memory on the single event upset-induced error rate of microprocessors

“…To Manuscript obtain the failure rate of the microprocessor executing a given program, the static cross-section is multiplied with the ratio between injected faults producing a corrupted output and the total number of fault injected. This method has been successfully applied to several simple processors [4] and with some restrictions to a complex one [5] but it has serious limitations when the targeted processor has significant hidden sensitive parts (cache memories for example), since it exploits processor instructions to inject faults and observe their effects.…”