Establishing fast, practical, full-chip ILT flows using machine learning

Cecil, Thomas; Braam, Kyle; Omran, Ahmed; Poonawala, Amyn; Shu, Jason; Vandam, Clark

doi:10.1117/12.2551425

Cited by 7 publications

(8 citation statements)

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“…Machine learning: Masks being created by ML models trained on ILT masks. This next shift in mask synthesis is underway today, both in incremental steps, as ML submodels of portions of the simulation system trained on more expensive rigorous physical solvers, and as full replacements of ILT, as deep ML models replicating the entire mask synthesis optimized solution. − Figure shows a representation of the MLILT model flow. The acceptance of and migration to these ML models in addition to optimization methods is underway and there are still many open questions.…”

Section: Newer Computational Toolsmentioning

confidence: 99%

Advances in Inverse Lithography

et al. 2022

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As Moore’s law has marched forward, progressively shrinking chip designs at a consistent pace, the manufacturing of those chips has raced to keep up. Through advances in lithography hardware and software, we now are in the realm of the single-digit-nanometer design nodes at leading chip foundries. This paper will review the method of Inverse Lithography Technology (ILT), which is the preferred computational method for photolithography. Indeed photolithographic masks were the first metasurfaces, and still the most important metasurface, economically, used in memory chips, storage, and microprocessors. Moreover, photolithographic mask designers were the early adopters of the mathematical optimization in optics, creating ILT, specifying intended wafer patterns and metrics, and using the mathematical machinery of level sets, functional derivatives, and adjoints to drive the mask design process.

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Section: Newer Computational Toolsmentioning

confidence: 99%

Advances in Inverse Lithography

et al. 2022

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“…Inspired by many success stories of ML in a broad range of artificial intelligence applications, both industrial and academic researchers are now actively developing ML solutions for challenging problems in computational lithography, including ILT. [99][100][101]121,[138][139][140] One of the first papers applying DL to ILT is from ASML Brion. Their 2017 paper shows how they use their freeform ILT engine to train an ILT DL model using a convolutional neural network (CNN) (Fig.…”

Section: Applying Deep Learning To Iltmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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“…Among these applications is the ML-accelerated ILT flow, which is critical to enable full chip mask synthesis with ILT and delivering unmatched results. In previous work 1 , it was demonstrated that machine learning models can replace much of the heavy lifting done by ILT solutions, resulting in TAT comparable to traditional RBAF+OPC with QoR similar to full ILT. The paper noticed the importance of selecting a small set of patterns to have good coverage of the full chip design.…”

Section: Introductionmentioning

confidence: 99%

“…2 shows a ML accelerated ILT mask synthesis flow. Related prior works include simple random sampling and geometrical pattern classification [1][2][3][4][5][6][7][8][9] , which generates geometrical representation of pattern clips in different forms and then forms groups by adopting different clustering algorithms. One full chip application 9 extracts a set of characteristic design patterns evenly distributed within the design space occupied by the layout sampling design, which is comprised of billions of patterns.…”

Section: Introductionmentioning

confidence: 99%

Automatic generation of representative and diversified pattern samples from a full chip layout

Zhu

Falch

Braam

et al. 2023

DTCO and Computational Patterning II

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To successfully transfer design patterns to wafer, it is essential to calibrate different types of models to describe the optical, physical, and chemical effects in chip manufacturing process. In recent years, there have also been active investigations of machine learning (ML) models to capture various aspects of semiconductor processes. As it is well known, model training time and model accuracy are heavily influenced by the input data. It is becoming increasingly important to provide highly efficient methods to automatically generate effective pattern samples from full chip designs. A straightforward approach, simple random sampling, can be highly efficient to generate effective samples for a homogeneous population. However, real world chip layouts are characterized by geometrical and lithographical feature distributions that vary significantly across the full chip design space. The complexity of the problem necessitates the adoption of a comprehensive set of approaches for sampling as well as flexibility in customizing the sampling strategy for various applications. In this paper, we investigate automatic layout sampling to optimize the coverage and diversity of patterns given the need for minimizing training sample size or other constraints, and therefore adopting various unsupervised learning techniques. The flow scales very well with computation resources to efficiently process full chip layouts. A simple, standard interface is provided for typical usage, but flexible programming APIs are available to customize the sampling strategy for advanced applications. Results demonstrate that the samples generated by this flow have increased diversity, which leads to significantly reduced model training time with comparable or increased model accuracy.

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Establishing fast, practical, full-chip ILT flows using machine learning

Cited by 7 publications

References 0 publications

Advances in Inverse Lithography

Advances in Inverse Lithography

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Automatic generation of representative and diversified pattern samples from a full chip layout

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