ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

Dai, Chia-Tsen; Ker, Ming‐Dou

doi:10.1109/ted.2016.2544382

Cited by 27 publications

(4 citation statements)

References 14 publications

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“…By combining these modifications, a significant improvement in FOM is verified. The figure of merit (FOM) is cited from [7] and defined as the tolerable power density of single device given by FOM=( V h · I t2 )/( N · W ) to evaluate the V h and I t2 performance of single device. Generally, accompanied by the improving of V h performance, it still causes the degradation of I t2 due to the higher-power dissipation.…”

Section: Structure and Mechanismmentioning

confidence: 99%

Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection

et al. 2019

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A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage ( V h ). Compared with the measured V h of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the V h of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current ( I t2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.

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Section: Structure and Mechanismmentioning

confidence: 99%

Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection

et al. 2019

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“…Therefore, it cannot provide an efficient output ESD protection alone. In order to optimize the I-V characteristics of the SCR, various methods have been proposed to improve the holding voltage of the SCR for medium-and high-voltage circuit (10 V/12 V/24 V/40 V) ESD protections [3][4][5][6][7][8][9]. However, the above methods will introduce higher turn-on resistance (R on ) and lower effective protection current (I eff ), or even additional fabrication cost.…”

Section: Introductionmentioning

confidence: 99%

A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process

Chen

Liu

Guo

et al. 2021

Semicond. Sci. Technol.

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In this paper, a novel robust low-voltage-triggered silicon-controlled rectifier (LVTSCR) with high holding voltage, low trigger voltage, and low overshoot voltage has been proposed for 5 V integrated circuit electrostatic discharge (ESD) protection. The new LVTSCR integrates an extra low-resistance current path by embedding an NMOS transistor into the traditional LVTSCR. This extra current path will divert part of the ESD current, thus resulting in a lower overshoot voltage as well as better quasi-static I–V characteristics in the new structure. As such, the holding voltage of the new LVTSCR has been increased by ∼23%, the quasi-static triggering characteristic has been decreased by ∼8%, and the overshoot voltage has been improved by ∼38%.

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“…Under high voltage conditions, the lack of protection capability limits traditional DDSCRs as an ESD protection device for the Bus interface. Various improvements have been proposed to adjust the DDSCR's ESD design window [10][11][12][13]. Obviously, these improved structures can effectively solve some problems existing in traditional DDSCRs, but their failure currents are not significantly improved.…”

Section: Introductionmentioning

confidence: 99%

Dual direction SCR with deep well structure for high voltage ESD in communication bus

Wang

Jin

Zheng

et al. 2019

Semicond. Sci. Technol.

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In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device's fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

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ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

Cited by 27 publications

References 14 publications

Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection

Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection

A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process

Dual direction SCR with deep well structure for high voltage ESD in communication bus

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