Escaped Boundary Pins Routing for High-Speed Boards

Chin, Ching-Yu; Kuan, Chung-Yi; Tsai, Tsung-Ying; Chen, Hung-Ming; Kajitani, Yoji

doi:10.1109/tcad.2012.2221714

Cited by 13 publications

(10 citation statements)

References 16 publications

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“…The solver used to solve the ILP model is Gurobi [25]. We used three test cases, case1-case3 from [14], where case3 has six buses. We have also tested the case from the BSG router in [13].…”

Section: Resultsmentioning

confidence: 99%

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

Tseng

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Length-matching is an important technique to balance delays of bus signals in high-performance printed circuit board (PCB) routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high-performance PCB designs.Index Terms-Dense meander segments, ILP model, printed circuit board (PCB) routing, speedup effect.

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Section: Resultsmentioning

confidence: 99%

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

Tseng

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…[17], [18]. However, this work used a greedy way to assign layers for pins and merge all multicomponents at the same time, which was not efficient.…”

Section: Related Workmentioning

confidence: 99%

“…As mentioned in Section 2, Refs. [17] and [18] introduced a method to solve the fixed disordered pins routing problem, which routes nets as many as possible in a current layer, and then routes crossing nets in added layers to release the crossings. In this paper, we adopt the similar idea but implement in different way.…”

Section: Proposed Routing Algorithmmentioning

confidence: 99%

“…Another difference is that, in the initial routing phase of Refs. [17] and [18], against-the-wall routing method is adopted, which may generate some long wires, and it increases the workload for wire length adjustment. In our method, single commodity flow is used for initial routing, and it makes the initial routing result easier for further adjustment.…”

Section: Proposed Routing Algorithmmentioning

confidence: 99%

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Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

Zhang

Pan

Zhu

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Abstract:In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.

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“…In addition, in [4] and [14], a practical approach to solve the fixed ordering boundary pin routing problem was discussed. However, it used a greedy way to assign layers for pins which was not efficient.…”

Section: Introductionmentioning

confidence: 99%

A length matching routing method for disordered pins in PCB design

Zhang

Pan

Zhu

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obtain a length matching routing. We initially check the longest common subsequence of pin pairs to assign layers for pins. Then, adopt single commodity flow to generate base routes. R-flip and C-flip are finally carried out to adjust the wire length. The experiments show that our algorithm generates the optimal routes with better wire balance within reasonable CPU times.

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Escaped Boundary Pins Routing for High-Speed Boards

Cited by 13 publications

References 16 publications

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

A length matching routing method for disordered pins in PCB design

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