A length matching routing method for disordered pins in PCB design

Zhang, Ran; Pan, Tieyuan; Zhu, Li; Watanabe, Takahiro

doi:10.1109/aspdac.2015.7059038

Cited by 6 publications

(4 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many studies in the literature have addressed these routing problems related to the PCBs. Some studies have proposed the heuristics algorithms to obtain a length matching routing (Zhang et al, 2015b) and others have used differential pair escape (Li et al, 2012(Li et al, , 2019, single signal escape routing (Wu & Wong, 2013) or both (Wang et al, 2014) for escape routing along with addressing the length matching problem. The most notable technique used for the PCB routing is optimization.…”

Section: Related Workmentioning

confidence: 99%

“…Many studies in the literature have proposed solutions for escape routing problem among which some have considered single layer (Lei & Mak, 2015) in the PCB while, multiple layers (Bayless, Hoos & Hu, 2016, Zhang et al, 2015a have also been considered. There are studies that only consider escape routing (McDaniel, Grissom & Brisk, 2014) while, there are some studies which consider other problems like length matching (Zhang et al, 2015b, Yan, 2015, Chang, Wen & Chang, 2019 along with the escape routing as well. Some have used staggered pin array (Ho, Lee & Chang, 2013; while others have used grid pin array (Jiao & Dong, 2016) as well.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

View full text Add to dashboard Cite

Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

View full text Add to dashboard Cite

show abstract

“…For example, Tian and Watanabe [2] considered the delay-matching constraint in bus routing to meet several timing specifications. Yan and Wong [3] and Zhang et al [4] handled the length-matching bus routing such that the wire lengths of all nets on the same bus are within the specified range. However, none of these works considered the constraint of maintaining the same topology for all bits on the same bus.…”

Section: Introductionmentioning

confidence: 99%

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

et al. 2021

View full text Add to dashboard Cite

As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.

show abstract

“…In Ref. [19], we already discussed the length matching routing for disordered pins in dense routing problems. However, the method for pin sets selection and wire length adjustment were not so efficient.…”

Section: Related Workmentioning

confidence: 99%

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

Zhang

Pan

Zhu

et al. 2015

IPSJ Transactions on System LSI Design Methodology

Self Cite

View full text Add to dashboard Cite

Abstract:In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.

show abstract

A length matching routing method for disordered pins in PCB design

Cited by 6 publications

References 18 publications

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

Contact Info

Product

Resources

About