Error propagation analysis using FPGA-based SEU-fault injection

Fast FPGA-based fault injection tool for embedded processors

“…This helps us for having fast fault injection experiments that is important for real time applications. However, halting processor is mostly used in scan chain based SEU fault injection methods [11].…”

“…One golden run is performed to have the reference for comparison. A method for running golden run and faulty experiment alternatively is also introduced in [11] but it is done for each clock until the unequal values are manifested. In our method, we perform golden run for several clocks and then we repeat it with same values for faulty experiment.…”

“…Fault injection is one important way for evaluating microprocessors and finding dependability parameters. Within numerous fault injection methods that have been proposed, there is four major groups: 1) software implemented fault injection [3][4][5] 2) physical fault injection [6] [7] 3) Simulation-based fault injection [8][9] 4) FPGAbased fault injection [10][11][12][13][14][15][16][17][18].…”

“…As an alternative way, FPGA can accelerate fault injection experiments and it can provide good controllability and observability as well. There are two major groups for FPGA-based fault injection methods [11]: 1) Reconfiguration-based Techniques 2) Instrumentationbased techniques.…”

“…In instrumentation-based techniques [10][11][12][13][ [15][16][17][18], extra circuits are added to the original circuits and both are located inside FPGA after getting synthesized. Although these methods do not have time overhead, they suffer from area overhead.…”