Error floor behavior study of LDPC codes for concatenated codes design

Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

“…First, at different SNRs, the residual error distribution of the LDPC code with the code rate of 0.5 and code length of 576 bits is illustrated in Figure 2, where k denotes the number of residual error bits occurring in the information bit part in the LDPC codeword after decoding, and P(k) denotes the occurrence probability of the codeword in which k information bits are erroneous. It can be observed that, though the number of residual error bits of the LDPC code is much less than the code length, it is still large compared with some special LDPC codes [19,20]. Therefore, the product code scheme is proposed to disperse the residual errors of LDPC codewords into various algebraic codewords.…”

“…The performance of the LDPC codes is affected by decoding algorithms and quantization methods [19,24]. Furthermore, in the case of extremely low error rate, software simulation is not practical for it will need a long period of simulation time [26].…”

“…One is to optimize the structure of LDPC codes or to improve the LDPC decoding algorithm, but the additional complexity brought by these two approaches is higher [16][17][18]. The other is to construct concatenated codes or product codes [15,[19][20][21]. Constructing concatenated codes requires that the outer code has great error correction capability due to the presence of abundant residual error bits in LDPC codewords, which causes the code rate loss of concatenated codes and further affects the overall performance.…”

“…We demonstrate that the performance of the proposed iterative decoding scheme obviously surpasses the performance of decoding scheme without iteration. Furthermore, considering software simulation is limited by time and equipment due to the requirements of longer code length and lower error floor, and the quantization method is an important factor for the performance of iterative decoding [19,24], the corresponding hardware decoder and the overall evaluation platform of the product code are implemented to further verify the proposed iterative decoding methods. Hardware experiment results show that the designed codec structure achieves a good trade-off between hardware complexity and throughput and thus effectively accelerates the performance evaluation.…”