Erasure-correction-enhanced iterative decoding for LDPC-RS product codes

Chen, Weigang; Wang, Ting; Han, Changeai; Yang, Jinsheng

doi:10.23919/jcc.2021.01.005

Cited by 11 publications

(10 citation statements)

References 35 publications

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“…We introduce perturbation decoding to enhance the proposed LDPC-RS concatenation scheme and eliminate the error floor. In [6], LDPC-RS product code and the hybrid error-erasure correction (HEEC) decoding algorithm were proposed. The difference is that our proposed approach utilizes concatenated code, i.e., a whole RS code word is treated as the information part of an LDPC code word.…”

Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

“…The difference is that our proposed approach utilizes concatenated code, i.e., a whole RS code word is treated as the information part of an LDPC code word. Additionally, [6] utilizes product code, in which multiple RS code words are put in columns and multiple LDPC codes are put in rows. LDPC (576, 288)-RS (255, 51) product code (code length 576 × 255) and HEEC decoding in [6] will have better performance than our proposed scheme.…”

Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

“…Additionally, [6] utilizes product code, in which multiple RS code words are put in columns and multiple LDPC codes are put in rows. LDPC (576, 288)-RS (255, 51) product code (code length 576 × 255) and HEEC decoding in [6] will have better performance than our proposed scheme. However, since product code is deeply coupled, RS decoding can only start after 255 LDPC codes finish decoding.…”

Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

“…However, an error floor phenomenon can be found with many LDPC codes; when SNR increases, the BER does not decrease, or the curve flattens. According to [6], the error floor [7] is caused by sub-optimal iterative decoding [8], near-code words [9], and absorbing and trapping sets [10]. In some situations, the error floor can not be eliminated, and there are some methods to lower the error floor, for example, designing a large-girth parity matrix to optimize the code structure; using concatenation code, such as RS-LDPC [11] or DVB BCH-LDPC code [12] that utilizes RS or BCH as the outer code and the LDPC as the inner code; or manually introducing lowmagnitude noise to message-passing decoders to lower the error floor.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

Shi,

Luo,

2024

Electronics

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Faster-than-Nyquist (FTN) signaling has attracted increasing interest in the past two decades. However, when the fifth-generation (5G) communication low-density parity check (LDPC) code is applied to FTN signaling with low Bahl–Cock–Jelinek–Raviv (BCJR) states of detection and few turbo equalization iterations, an error floor near 10−5 is found, which does not exist in the original LDPC used for orthogonal signaling. This can be eliminated through many detection and decoding iterations, but this is unacceptable considering the increase in latency and storage. To solve this problem, we propose an LDPC and Reed–Solomon (RS) concatenation code, shortening, and perturbation scheme to lower the error floor. We propose a parallel encoder architecture for RS component code and a concise algorithm to calculate its constant multiplier coefficients, leveraging a traditional serial encoder, which can also be used for other parallelisms, rates, and lengths. The simulation results show that the proposed concatenation and shortening scheme can lower the error floor to about 10−7. The proposed scheme has an error correction capability for coded FTN signaling and successfully lowers the error floor with the limitation of few turbo iterations and few BCJR states.

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Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

Section: Performance Evaluation Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

Shi,

Luo,

2024

Electronics

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“…Erasure coding (EC), which originated in the 1960s, is an encoding method designed to enhance the fault tolerance of data transmission [23]. Initially developed to address data loss issues during network transmission in the communications field [24], its core idea involves subdividing the transmission signal and incorporating a verification mechanism, thereby creating interconnections among the signals. A notable characteristic is that even if part of the signal is lost during transmission, the receiving end can still reconstruct the complete information content using this algorithm.…”

Section: Background and Related Workmentioning

confidence: 99%

Symmetrical Data Recovery: FPGA-Based Multi-Dimensional Elastic Recovery Acceleration for Multiple Block Failures in Ceph Systems

Lei,

Wang,

Chen

et al. 2024

Symmetry

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In the realm of Ceph distributed storage systems, ensuring swift and symmetrical data recovery during severe data corruption scenarios is pivotal for data reliability and system stability. This paper introduces an innovative FPGA-based Multi-Dimensional Elastic Recovery Acceleration method, termed AMDER-Ceph. Utilizing FPGA technology, this method is a pioneer in accelerating erasure code data recovery within such systems symmetrically. By harnessing the parallel computing power of FPGAs and optimizing Cauchy matrix binary operations, AMDER-Ceph significantly enhances data recovery speed and efficiency symmetrically. Our evaluations in real-world Ceph environments show that AMDER-Ceph achieves up to 4.84 times faster performance compared with traditional methods, especially evident in the standard 4 MB block size configurations of Ceph systems.

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Improved forward error correction technology of RS-LDPC cascade code in optical transport network

Ma,

Shan

2023

Optoelectron. Lett.

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Erasure-correction-enhanced iterative decoding for LDPC-RS product codes

Cited by 11 publications

References 35 publications

An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling

Symmetrical Data Recovery: FPGA-Based Multi-Dimensional Elastic Recovery Acceleration for Multiple Block Failures in Ceph Systems

Improved forward error correction technology of RS-LDPC cascade code in optical transport network

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