Error detection and correction in semiconductor memories using 3D parity check code with hamming code

Tambatkar, Shivani; Menon, Sreedevi K.; Sudarshan, V.; Vinodhini, M.; Murty, N. S.

doi:10.1109/iccsp.2017.8286516

Cited by 25 publications

(10 citation statements)

References 7 publications

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“…Practically the data along with parity bits called as code word is written into memory and the error evaluation is performed for data read from memory. One among them is 3D parity check codes [1] whose usual way of data representation is indicated in figure 3 for representation of matrix [17][18][19] [20], where the H-Bits, V-Bits and D-Bits indicate the Horizontal, Vertical and the Diagonal Parity Bits respectively. Fig.…”

Section: Existing Matrix Codesmentioning

confidence: 99%

“…8. Refined candidate bits obtained from the final step [4] In [1], the same matrix in 8x8 data representation is modified into a 4x16 matrix [22]. It uses 39 parity bits i.e., 4 H bits, 16 V bits and 19 D bits.…”

Section: Fig4 3d Parity Check Code Using 8x8 Matrix Representationmentioning

confidence: 99%

“…Among these this paper focuses on adjacent error correction. The generic block requires a knowledge which is encoded in required format before writing into the memory and later after read operation, the info is decoded and verified with parity bits for correcting possible errors [1]. Here 3PC represents the three dimensional redundant check code where the 3D redundant check codes (i.e., Horizontal, Vertical and Diagonal Parity Codes) are encoded and these are again encoded in HVHC i.e., Horizontal Vector Hamming Code encoder which again calculates the hamming code parity bits.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Half diagonal matrix codes for reliable embedded memories

Neelima

Subhas

2022

ijhs

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Reliability of embedded memories is dependent on at-speed rated correction capability of error detection and correction codes. Many critical applications like medical databases, rocket launch details stored in memories require accurate data and which cause major human losses or economy losses even if a 1% of data is compromised. This paper focuses on developing improved reliable error detection and correction codes with minimum redundant bits and maximum code rate. The decoder uses the concept of Encoder Reuse Technique along with the Modulo-2 addition to calculate syndrome, error location and correction of data bits when data is read from memory. The codes are represented in verilog hardware description language and simulated in the Tool Xilinx ISE 14.5 for XC7Z020-1CLG484 FPGA. The codes are evaluated for their performance in terms of technology parameters like area, delay, power, power – delay product, etc. Also for other parameters like bit overhead, code rate, code efficiency, correction coverage, correction efficiency, etc and correction coverage per cost for combined evaluation. The implemented half diagonal code is more effective as compared to existing matrix codes, it reduces bit overhead at least by 5.5% to 46.96% and coding rate increased at least by 16.74% to 23.85%.

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Section: Existing Matrix Codesmentioning

confidence: 99%

Section: Fig4 3d Parity Check Code Using 8x8 Matrix Representationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Half diagonal matrix codes for reliable embedded memories

Neelima

Subhas

2022

ijhs

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“…The transmission systems are exposing to get bits error values in either the instruction or data causing undesirable crashes or other system failures. Therefore, utilizing Hamming Code inside an embedded system is considered with high priority in modern industrial fields [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

“…Hamming code as hardware system using VHDL or Virlog as hardware description language is proposed to demonstrate and analyze the performance of the system. Most of these works have limitation on the number of data bits and hardware resources [7][8][9][10][11][12][13][14][15][16][17][18][19]. Literary review for the most important research involved this approaches with their limitation can be summarized: -ECC application on embedded systems is designed for memory error detection and correction it is realized a 64-bit ECC controller has been proposed in [10].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of single bit error correction linear block code system based on FPGA

Hamdoon¹,

Mohammed²,

Mohammed³

2019

TELKOMNIKA

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Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate.

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Multiple Adjacent Bit Error Detection and Correction Codes for Reliable Memories: A Review

Neelima

Subhas

2021

Lecture Notes in Electrical Engineering

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Error detection and correction in semiconductor memories using 3D parity check code with hamming code

Cited by 25 publications

References 7 publications

Half diagonal matrix codes for reliable embedded memories

Half diagonal matrix codes for reliable embedded memories

Design and implementation of single bit error correction linear block code system based on FPGA

Multiple Adjacent Bit Error Detection and Correction Codes for Reliable Memories: A Review

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