Erasure generation and interleaving for meteor-burst communications with fixed-rate and variable-rate coding

Baum, C.W.; Wilkins, C.S.

doi:10.1109/26.592591

Cited by 6 publications

(2 citation statements)

References 11 publications

(9 reference statements)

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“…A key part of using an RS decoding system with multiple erasure generators is the determination of appropriate Motivated by Baysian decision theory [5], the erasure flag for a given received symbol r = (r0, r1, . .…”

Section: Multiple Erasure Generators and Component Decodersmentioning

confidence: 99%

“…For errors-and-erasures RS decoders, the determination of e(x) takes place in two separate steps. Initially, in the erasure generator, sampled data symbols are compared against prespecified error thresholds using Baysian decision theory [4] [5]. The erasure threshold then generates a one-bit erasure flag per symbol to indicate to the subsequent component decoder if the symbol should be ignored.…”

Section: Introductionmentioning

confidence: 99%

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An adaptive Reed-Solomon errors-and-erasures decoder

Atieno

Allen

Goeckel

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamicallyreconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder power consumption. Algorithm parameters for the decoding system have been determined via simulation and the design has been implemented in Altera Stratix FPGAs. Through experimentation using an Altera 1S40 Stratix FPGA, we show that dynamic reconfiguration can result in an 14% performance improvement versus a non-reconfigurable decoder implementation. Comparisons with a Pentium IV microprocessor illustrate five orders of magnitude performance improvement.

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Section: Multiple Erasure Generators and Component Decodersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%