An adaptive Reed-Solomon errors-and-erasures decoder

Abstract

The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamicallyreconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder power consumption. Algorithm parameters for the decoding system have been determined via simulation and the design has been implemented in Altera Stratix FPGAs. Through experimentation using an Altera 1S40 Stratix FPGA, we show that dynamic reconfiguration can result in an 14% performance improvement versus a non-reconfigurable decoder implementation. Comparisons with a Pentium IV microprocessor illustrate five orders of magnitude performance improvement.

Sorting on architecturally diverse computer systems

“…Manufacturers are also tailoring FPGAs to the needs of different application areas, including optional embedded processor cores, multiplyaccumulate units, specialized I/O functionality, etc. Carefully architecting an FPGA design can lead to a large speedup over a general-purpose processor in many non-trivial applications [2,3,9,18,26,27]. El-Ghazawi et al [10] recently published a comprehensive discussion of the applicability of FPGAs to high-performance computing.…”

Flares

“…It therefore communicates with the Linux Memory Technology Device (MTD) that acts as a device driver interfacing the file system with the NAND flash controller. In a real environment, the NAND flash controller manages the flash operations and performs ECC encoding and decoding exploiting fast ECC hardware structures such as the ones presented in Zambelli et al [2012], Di Carlo Atieno et al [2006], and Chen et al [2009]. To perform controlled experiments in which errors can be easily emulated and realistic performance precisely measured, the full hardware layer reported in Figure 2 has been emulated at the MTD level.…”

“…ECCs with programmable correction capability are now widely implemented in the same flash controller to adapt the error rate changes over program and erase cycles. This trend is confirmed by an increased number of publications proposing hardware implementations of adaptable BCH and RS codecs for NAND flash that guarantee low hardware overhead compared to worst-case designs that implement a fixed correction capability [Song et al 2002;Atieno et al 2006;Chen et al 2009;Caramia et al 2010;Cherukuri 2010;Zambelli et al 2012;Fabiano et al 2013]. However, for a realistic application of an adaptable ECC to a NAND flash, a strategy to decide which correction capability to use at runtime is required.…”

Application development on hybrid systems

“…Even with the above obstacles to efficient use of application developer time, performance gains have been demonstrated on real applications executing on hybrid systems, e.g., see [1,2,5,6,7,9,12,13,14,16,17,20,21,24]. Example applications that can benefit from hybrid system architectures include signal processing, biosequence search, encryption, text search, etc.…”