Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases

Pruss, Tim; Kalla, Priyank; Enescu, Florian

doi:10.1145/2593069.2593134

Cited by 24 publications

(40 citation statements)

References 14 publications

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“…These methods model the arithmetic circuit specification and its hardware implementation as polynomials [13], [14], [15], [16], [17], [18]. They attempt to prove that the implementation satisfies the specification by performing a series of divisions of the specification polynomial F by the implementation polynomials B = {f1, .…”

Section: Related Workmentioning

confidence: 99%

“…al [17,18], formulated the verification problem similarly, but applied it to Galois field (GF) arithmetic circuits, which enjoy certain simplifying properties. Specifically, for GF, the problem reduces to the ideal membership testing over a larger ideal that includes J0 = x 2 − x in F2.…”

Section: Related Workmentioning

confidence: 99%

“…The solution uses a modified Gaussian elimination technique. In [18], a symbolic computer algebra method is used to derive a word level abstraction for GF circuits, where GF operators are elements of a polynomial ring with coefficients in F 2 k . This work relies on the customized computation of Groebner basis and applies only to GF networks.…”

Section: Related Workmentioning

confidence: 99%

“…In contrast to [22], it works directly on unstructured, gate-level implementations. And in contrast to [16], [18] and other computer algebra methods, it is done using efficient polynomial transformation process, without a need for expensive Groebnerbased polynomial division.…”

Section: Function Extractionmentioning

confidence: 99%

“…The functional abstraction technique described in[18] applies only to Galois field circuits and is based on polynomial reduction via Groebner basis.…”

mentioning

confidence: 99%

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Verification of gate-level arithmetic circuits by function extraction

Ciesielski

Brown

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract the arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 Million gates. The procedure has linear runtime and memory complexity, measured by the number of logic gates.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Function Extractionmentioning

confidence: 99%

“…The functional abstraction technique described in[18] applies only to Galois field circuits and is based on polynomial reduction via Groebner basis.…”

mentioning

confidence: 99%

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Verification of gate-level arithmetic circuits by function extraction

Ciesielski

Brown

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Incremental column-wise verification of arithmetic circuits using computer algebra

Kaufmann

Biere

Kauers

2019

Form Methods Syst Des

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Verifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning over pseudo boolean polynomials. In this approach a word-level specification is reduced by a Gröbner basis which is implied by the gate-level representation of the circuit. This reduction returns zero if and only if the circuit is correct. We give a rigorous formalization of this approach including soundness and completeness arguments. Furthermore we present a novel incremental column-wise technique to verify gate-level multipliers. This approach is further improved by extracting full-and half-adder constraints in the circuit which allows to rewrite and reduce the Gröbner basis. We also present a new technical theorem which allows to rewrite local parts of the Gröbner basis. Optimizing the Gröbner basis reduces computation time substantially. In addition we extend these algebraic techniques to verify the equivalence of bit-level multipliers without using a word-level specification. Our experiments show that regular multipliers can be verified efficiently by using off-the-shelf computer algebra tools, while more complex and optimized multipliers require more sophisticated techniques. We discuss in detail our complete verification approach including all optimizations.

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The specifics of the Galois field GF(257) and its use for digital signal processing

Bakirov,

Matrassulova,

Vitulyova

et al. 2024

Sci Rep

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An algorithm of digital logarithm calculation for the Galois field $$GF(257)$$ G F ( 257 ) is proposed. It is shown that this field is coupled with one of the most important existing standards that uses a digital representation of the signal through 256 levels. It is shown that for this case it is advisable to use the specifics of quasi-Mersenne prime numbers, representable in the form $${p=2}^{n}+1$$ p = 2 n + 1 , which includes the number 257. For fields $$GF({2}^{n}+1)$$ G F ( 2 n + 1 ) , an alternating encoding can be used, in which non-zero elements of the field are displayed through binary characters corresponding to the numbers + 1 and − 1. In such an encoding, multiplying a field element by 2 is reduced to a quasi-cyclic permutation of binary symbols (the permuted symbol changes sign). Proposed approach makes it possible to significantly simplify the design of computing devices for calculation of digital logarithm and multiplication of numbers modulo 257. A concrete scheme of a device for digital logarithm calculation in this field is presented. It is also shown that this circuit can be equipped with a universal adder modulo an arbitrary number, which makes it possible to implement any operations in the field under consideration. It is shown that proposed digital algorithm can also be used to reduce 256-valued logic operations to algebraic form. It is shown that the proposed approach is of significant interest for the development of UAV on-board computers operating as part of a group.

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Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases

Cited by 24 publications

References 14 publications

Verification of gate-level arithmetic circuits by function extraction

Verification of gate-level arithmetic circuits by function extraction

Incremental column-wise verification of arithmetic circuits using computer algebra

The specifics of the Galois field GF(257) and its use for digital signal processing

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