Incremental column-wise verification of arithmetic circuits using computer algebra

Abstract

Verifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning over pseudo boolean polynomials. In this approach a word-level specification is reduced by a Gröbner basis which is implied by the gate-level representation of the circuit. This reduction returns zero if and only if the circuit is correct. We give a rigorous formalization of this approach including soundness and completeness arguments. Furthermore we present a novel incremental column-wise technique to verify gate-level multipliers. This approach is further improved by extracting full-and half-adder constraints in the circuit which allows to rewrite and reduce the Gröbner basis. We also present a new technical theorem which allows to rewrite local parts of the Gröbner basis. Optimizing the Gröbner basis reduces computation time substantially. In addition we extend these algebraic techniques to verify the equivalence of bit-level multipliers without using a word-level specification. Our experiments show that regular multipliers can be verified efficiently by using off-the-shelf computer algebra tools, while more complex and optimized multipliers require more sophisticated techniques. We discuss in detail our complete verification approach including all optimizations.

SAT, Computer Algebra, Multipliers

“…Our incremental algorithm is shown in Alg. 1 and it follows from the proof of Thm.6 in [13] that Alg. 1 is correct.…”

“…We discuss the implementation of AMULET and present the underlying algorithms of [14] in more detail. Additionally we provide a generalization of our incremental approach of [13]. We further show that we are able to generate proof certificates of quadratic length for simple multipliers.…”

“…In [13] we introduced an incremental verification algorithm, which splits the verification problem into smaller more manageable subproblems by partitioning the circuit into column-wise slices and splitting the word-level specification into multiple smaller specifications which relate the partial products, incoming carries, sum output bit and the outgoing carries of each slice. However this algorithm is tailored to multiplication of unsigned bit-vectors.…”

“…Currently the most successful automated approach uses polynomial reasoning [4,13,17,18,23] and in recent years has seen significant progress. The approach of [17,18] employs local cancellation of vanishing monomials in converging cones, which allows to verify a large variety of multiplier architectures much more efficiently than previous work.…”

“…This paper provides supplementary material for an invited talk at Vampire'19 of the second author based on [13,14]. We discuss the implementation of AMULET and present the underlying algorithms of [14] in more detail.…”