Equidistance routing in high-speed VLSI layout design

Kubo, Yukiko; Miyashita, Hiroshi; Kajitani, Yoji; Tateishi, Kazuyuki

doi:10.1145/988952.989005

Cited by 7 publications

(6 citation statements)

References 3 publications

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“…On length matching of wires for conventional ICs and printed circuit boards (PCBs), recent studies [8][9][10][11][12] tried to minimize either length difference or length-ratio difference among a set of nets during routing. Such problem formulation cannot meet the stringent routing requirements of microstrip lines in mm-wave CMOS RFICs because the length of each microstrip line after routing must be exactly the same as the given length at the circuit design to maintain the expected RF circuit performance.…”

Section: Previous Workmentioning

confidence: 99%

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Tseng

Yeh

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to generate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to half an hour.

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Section: Previous Workmentioning

confidence: 99%

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Tseng

Yeh

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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“…For the determination of a better length matching target. Kubo et al [1] approached length matching with a symmetric slant grid interconnect scheme to prevent a too-large target length. Nakatani et al [11] was dedicated to optimizing raw trace before length matching by employing a minimum cost maximum flow algorithm to reduce the maximum trace length while keeping the minimum total trace length.…”

Section: A Related Workmentioning

confidence: 99%

“…where Req j denotes the required space for trace j. Here, we employ a Linear Programming (LP) problem to solve this assignment: Assignment Problem: find: feasible x ij satisfying: neighbor validity constraint (1) feasibility constraint (2) sufficiency constraint (3) (4) This assignment scheme ensures the preserved original routing is contained in the rouTable area for the following stages. Some techniques of existing works can help to figure out a better routing if the LP is infeasible [21].…”

Section: Region Assignmentmentioning

confidence: 99%

Obstacle-aware length-matching bus routing

Yan

Chen

2011

Proceedings of the 2011 International Symposium on Physical Design

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As clock frequency increases, signal propagation delay on PCBs is requested to meet the timing specification with very high accuracy. Generally speaking, the net length in a single layer can estimate the routing delay in a single-layer net. In this paper, given a set of r single-layer nets in a bus with their length constraints inside mxn routing grids with s obstacle grids, based on obstacle-aware region partition inside routing grids, obstacle-aware shortest path generation and two detouring operations, R-flip and C-flip, an efficient O(mn+s 3 ) algorithm is proposed to generate the length-matching paths for obstacle-aware bus routing. Compared with the published CAFE router, our proposed routing algorithm can save 80.5% of CPU time to complete obstacle-aware length-matching bus routing with no length error for tested examples on the average.

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“…In [11] the delay matching problem is solved by using a Lagrangian model to allocate resources for wire snaking. In [12] this problem is solved with the help of slant symmetric grids. The method in [13] transforms this length matching task to an area assignment problem and proposes a gridless framework using boundedsliceline grids.…”

Section: Introductionmentioning

confidence: 99%

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

Tseng

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Length-matching is an important technique to balance delays of bus signals in high-performance printed circuit board (PCB) routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high-performance PCB designs.Index Terms-Dense meander segments, ILP model, printed circuit board (PCB) routing, speedup effect.

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Equidistance routing in high-speed VLSI layout design

Cited by 7 publications

References 3 publications

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Obstacle-aware length-matching bus routing

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing

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