Epitaxially grown Si/SiGe interband tunneling diodes with high room-temperature peak-to-valley ratio

Duschl, R.; Schmidt, Oliver G.; Eberl, K.

doi:10.1063/1.125616

Cited by 41 publications

(21 citation statements)

References 10 publications

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“…9,10 This Letter describes recent progress in the low temperature encapsulation of phosphorus dopants in silicon and represents one of the first demonstrations of P δ-doping using phosphine gas as the dopant source.…”

Section: 4mentioning

confidence: 99%

“…9 This has only recently been demonstrated in the fabrication of SiGe tunneling diodes, where P δ-doped layers are fabricated with a GaP solid dopant source. 9,10 This Letter describes recent progress in the low temperature encapsulation of phosphorus dopants in silicon and represents one of the first demonstrations of P δ-doping using phosphine gas as the dopant source. 11 The use of phosphine (PH 3 ) gas has previously been shown -with the deposition of a hydrogen resist layer and atomic lithography using a scanning tunneling microscopy (STM) tip -to allow atomic precision doping of the Si surface.…”

mentioning

confidence: 99%

“…9,10 These devices are of great interest for digital and high frequency applications due to their negative differential resistance. However, high peak to valley current ratios of about 5 have to be achieved for realistic applications, which requires minimal diffusion of the dopants in the device.…”

mentioning

confidence: 99%

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Encapsulation of phosphorus dopants in silicon for the fabrication of a quantum computer

Oberbeck

Curson

Simmons

et al. 2002

Applied Physics Letters

136

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The incorporation of phosphorus in silicon is studied by analyzing phosphorus δ-doped layers using a combination of scanning tunneling microscopy, secondary ion mass spectrometry and Hall effect measurements. The samples are prepared by phosphine saturation dosing of a Si(100) surface at room temperature, a critical annealing step to incorporate phosphorus atoms, and subsequent epitaxial silicon overgrowth. We observe minimal dopant segregation (~5 nm), complete electrical activation at a silicon growth temperature of 250 °C and a high two-dimensional electron mobility of ~10 2 cm 2 /Vs at a temperature of 4.2 K. These results, along with preliminary studies aimed at further minimizing dopant diffusion, bode well for the fabrication of atomically precise dopant arrays in silicon such as those found in recent solid-state quantum computer architectures. From Moore's Law it is well-known that the number of transistors on a chip doubles approximately every 18 months.1 In order to maintain this trend alternative means of fabricating devices are actively being pursued 2 and it is clear that the ability to fabricate atomically precise structures in silicon is becoming increasingly important. It is also important to characterize the spatial and electrical distribution of the dopant atoms. This is especially the case for a number of proposals to fabricate atomically precise dopant arrays in silicon for the fabrication of silicon based quantum computers. [3][4][5] In these architectures the dopant atom is required to be electrically active. The free electron of each dopant can then either act directly as the quantum bit 5 or mediate the coupling between quantum bits. 3,4Recent results have demonstrated that a precise array of phosphorus bearing molecules can be fabricated on a silicon surface using a hydrogen resist based strategy. 6 The next important step for creating ordered dopant arrays in silicon devices, which has not yet been demonstrated, is to encapsulate the dopants in high quality epitaxial silicon without disturbing the array. This step must aim at choosing an optimal substrate temperature to minimize dopant diffusion and surface segregation during growth, while maintaining a high structural quality of the epitaxial layer.While numerous publications exist on B and Sb δ-doping in Si, 7,8 P δ-doping has been applied only recently to the fabrication of SiGe tunneling diodes.9,10 These devices are of great interest for digital and high frequency applications due to their negative differential resistance. However, high peak to valley current ratios of about 5 have to be achieved for realistic applications, which requires minimal diffusion of the dopants in the device.9 This has only recently been demonstrated in the fabrication of SiGe tunneling diodes, where P δ-doped layers are fabricated with a GaP solid dopant source. 9,10 This Letter describes recent progress in the low temperature encapsulation of phosphorus dopants in silicon and represents one of the first demonstrations of P δ-doping using phosphine gas a...

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Section: 4mentioning

confidence: 99%

mentioning

confidence: 99%

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Encapsulation of phosphorus dopants in silicon for the fabrication of a quantum computer

Oberbeck

Curson

Simmons

et al. 2002

Applied Physics Letters

136

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“…To investigate the characteristics of sidewall GaAs tunnel junctions with narrower junction depths, both p + and n + -GaAs of MLE layers were thinned using a H 2 SO 4 The number and voltage positions of sharp steps in the NDR region change with the junction depth [102,103]. Three V S are observed when the junction depth is d = 50 nm, as shown in figure 12(a).…”

Section: Fine Structures In Quantum-confined Sidewall Gaas Tunnel Junmentioning

confidence: 99%

“…Later, tunnel junctions have been fabricated using Si [2,3], Si/SiGe [4,5], GaAs [6][7][8][9][10][11][12][13][14][15], InAs/Si [16], GaInAs/GaInNAs [17], InP/InGaAs [18], GaAsSb/InGaAs [19] and InAsP/GaAsP [20]. These tunnel junctions found numerous applications.…”

Section: Introductionmentioning

confidence: 99%

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Ohno

Oyama

2012

Science and Technology of Advanced Materials

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In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm −2 . They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.

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