2006
DOI: 10.1109/tcad.2005.855933
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Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines

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Cited by 26 publications
(12 citation statements)
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“…[3], [7]) by exploiting the decoding structure of the ROM. In the sequel we shall present the design of the decoder used in the ROM and its exploitation for the proposed scheme.…”
Section: Proposed Schemementioning
confidence: 99%
See 2 more Smart Citations
“…[3], [7]) by exploiting the decoding structure of the ROM. In the sequel we shall present the design of the decoder used in the ROM and its exploitation for the proposed scheme.…”
Section: Proposed Schemementioning
confidence: 99%
“…Input vector monitoring concurrent BIST techniques [2]- [7] have been proposed to avoid this performance degradation. These architectures test the Circuit Under Test (CUT) concurrently with its normal operation by exploiting input vectors appearing to the inputs of the CUT; if the incoming vector belongs to a set called active test set, the Response Verifier is enabled to capture the CUT response.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…During code definition and the synthesis of the prediction logic additional objectives can be followed: For example, concurrent error detection with parity codes has been extended to fault diagnosis and error correction [1], and the approaches in [2] and [19] target a low power implementation. Some other techniques try to detect just as many errors as possible at lower overhead.…”
Section: Code Definition and Parity Predictionmentioning
confidence: 99%
“…As the checker must be self-checking, cascadable two-rail checkers with six logic gates may be used to build the checker for parity groups [27]. As the results in [9] show, the resulting circuit is fault secure with an area overhead which is significantly lower than the overhead for the approaches reported in the literature so far [2,31].…”
Section: Code Synthesismentioning
confidence: 99%