Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions

Kakoee, Mohammad Reza; Riazati, Mohammad; Mohammadi, Siamak

doi:10.1109/isqed.2008.4479731

Cited by 7 publications

(4 citation statements)

References 8 publications

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“…Previous work has also introduced in-circuit assertions via hardware assertion checkers for each assertion in a design. Tools targeted at ASIC design provide assertion checkers using SVA [10], PSL [11], and OVL [12]. Academic tools such as Camera's debugging environment [13] and commercial tools such as Temento's DiaLite also provide assertion checkers for HDL.…”

Section: Related Researchmentioning

confidence: 99%

“…Academic tools such as Camera's debugging environment [13] and commercial tools such as Temento's DiaLite also provide assertion checkers for HDL. Kakoee et al show that in-circuit assertions [12] can also improve reliability, with a higher fault coverage than Triple Modular Redundancy (TMR) for a FIR filter and a Discrete Cosine Transform (DCT).…”

Section: Related Researchmentioning

confidence: 99%

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High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

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Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

show abstract

Section: Related Researchmentioning

confidence: 99%

Section: Related Researchmentioning

confidence: 99%

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

View full text Add to dashboard Cite

show abstract

“…Previous work has also introduced in-circuit assertions via hardware assertion checkers for each assertion in a design. Tools targeted at ASIC design provide assertion checkers using SVA [9], PSL [10], and OVL [11]. Academic tools such Camera's debugging environment [12] and commercial tools such as Temento's DiaLite also provide assertion checkers for HDL.…”

Section: Related Researchmentioning

confidence: 99%

“…Academic tools such Camera's debugging environment [12] and commercial tools such as Temento's DiaLite also provide assertion checkers for HDL. Kakoee et al show that in-circuit assertions [11] can also improve reliability, with a higher fault coverage than Triple Modular Redundancy (TMR) for a FIR filter and a Discrete Cosine Transform (DCT).…”

Section: Related Researchmentioning

confidence: 99%

High-level synthesis techniques for in-circuit assertion-based verification

Curreri

Stitt

George

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Field-Programmable Gate Arrays (FPGAs) are increasingly employed in both high-performance computing and embedded systems due to performance and power advantages compared to microprocessors. However, widespread usage of FPGAs has been limited by increased design complexity. Highlevel synthesis has reduced this complexity but often relies on inaccurate software simulation or lengthy register-transfer-level simulations for verification and debugging, which is unattractive to software developers. In this paper, we present high-level synthesis techniques that allow application designers to efficiently synthesize ANSI-C assertions into FPGA circuits, enabling realtime verification and debugging of circuits generated from highlevel languages, while executing in the actual FPGA environment. Although not appropriate for all systems (e.g., safety-critical systems), the proposed techniques enable software developers to rapidly verify and debug FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by less than 0.13% for several application case studies on an Altera Stratix-II EP2S180 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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On reusability of verification assertions for testing

Jenihhin

Raik

Ubar

et al. 2008

2008 11th International Biennial Baltic Electronics Conference

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Assertions have proven to be an effective mechanism to improve quality and to speed-up simulationbased design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing testing phase to increase the test quality and efficiency. The paper considers different types of design properties created for verification such as environmental assumptions and internal signal assertions. The reusable information is proposed to be applied for test pattern generation, embedded test observability improvement and DfT (design for testability) enhancement.

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Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions

Cited by 7 publications

References 8 publications

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

High-level synthesis techniques for in-circuit assertion-based verification

On reusability of verification assertions for testing

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