Enhancing Sensor Network Security with Improved Internal Hardware Design

Abstract

With the rapid development of the Internet-of-Things (IoT), sensors are being widely applied in industry and human life. Sensor networks based on IoT have strong Information transmission and processing capabilities. The security of sensor networks is progressively crucial. Cryptographic algorithms are widely used in sensor networks to guarantee security. Hardware implementations are preferred, since software implementations offer lower throughout and require more computational resources. Cryptographic chips should be tested in a manufacturing process and in the field to ensure their quality. As a widely used design-for-testability (DFT) technique, scan design can enhance the testability of the chips by improving the controllability and observability of the internal flip-flops. However, it may become a backdoor to leaking sensitive information related to the cipher key, and thus, threaten the security of a cryptographic chip. In this paper, a secure scan test architecture was proposed to resist scan-based noninvasive attacks on cryptographic chips with boundary scan design. Firstly, the proposed DFT architecture provides the scan chain reset mechanism by gating a mode-switching detection signal into reset input of scan cells. The contents of scan chains will be erased when the working mode is switched between test mode and functional mode, and thus, it can deter mode-switching based noninvasive attacks. Secondly, loading the secret key into scan chains of cryptographic chips is prohibited in the test mode. As a result, the test-mode-only scan attack can also be thwarted. On the other hand, shift operation under functional mode is disabled to overcome scan attack in the functional mode. The proposed secure scheme ensures the security of cryptographic chips for sensor networks with extremely low area penalty.

Scan‐based attack tolerance with minimum testability loss: a gate‐level approach

“…(i) conditional probability of observing hamming weight of 9, 12, 23 or 24 at protected scan cells and (ii) conditional probability of observing hamming weight of 9, 12, 23, or 24 at unprotected scan cells. These two terms can be calculated by (3) and (4), respectively P(HW (9,12,23,24) HW ∈ protected cells) × P(protected cells)…”

“…advanced encryption standard (AES) [10,[12][13][14], data encryption standard (DES) [9,11], and Rivest-Shamir-Adleman [15,16]. On the other hand, there are several countermeasures which attempt to protect crypto-chips against scan-based attacks in different ways such as mirror key register (MKR) [10], round register masking [14], state-dependent scan flip-flop (SDSFF) [15,16], dynamic obfuscation lock & key [17], on-chip key comparison [18,19], physically unclonable function (PUF)-based lock & key [20], dynamic scan [21], dynamic-key [22], dynamic obfuscation scan (DOS) [23], and key masking [24,25]. However, such countermeasures for scan-based attack tolerance suffer from one or more drawbacks which are described in the next section.…”

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

“…This can be reshuffled only after the system reset. Another countermeasure based on protection of cipher key is proposed in [30] for boundary scan design. These countermeasures in [28,29,30] are resistant to test-mode-only attack, but they also cause that the faults on the round key generation unit cannot be detected and thus reduce the reliability of cryptographic chips that pass the testing.…”

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

“…It is required that inserting the encryption hardware composed of the internal registers in the scan-chain architectures. The secure scan architecture of the cryptographic circuit reduces controllability and observability [ 11 , 12 ], reducing the accuracy of scan-chain diagnosis. Consequently, scan-chain diagnosis has become a crucial issue in semiconductor manufacturing for cryptographic circuits.…”