Enhancing Precision and Bandwidth in Cloud Computing: Implementation of a Novel Floating-Point Format on FPGA

Hou, Junjie; Zhu, Yongxin; Shen, Yulan; Li, Mengjun; Wu, Qian; Wu, Han

doi:10.1109/cscloud.2017.22

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…In that work, the authors showed a save of 80% of storage space with respect the use of Floats, without loosing in accuracy. • Hardware implementations: Type-I Unums have been recently implemented in hardware, on FPGA [16,22]. The authors conclude that implementing in hardware Type-I Unums requires a bigger area than that of an FPU.…”

Section: A Type-i Unumsmentioning

confidence: 99%

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

Cococcioni

Ruffaldi²,

Saponara

2018

2018 International Conference of Electrical and Electronic Technologies for Automotive

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This paper discusses the introduction of an integrated Posit Processing Unit (PPU) as an alternative to Floating-point Processing Unit (FPU) for Deep Neural Networks (DNNs) in automotive applications. Autonomous Driving tasks are increasingly depending on DNNs. For example, the detection of obstacles by means of object classification needs to be performed in real-time without involving remote computing. To speed up the inference phase of DNNs the CPUs on-board the vehicle should be equipped with co-processors, such as GPUs, which embed specific optimization for DNN tasks. In this work, we review an alternative arithmetic that could be used within the co-processor. We argue that a new representation for floating point numbers called Posit is particularly advantageous, allowing for a better trade-off between computation accuracy and implementation complexity. We conclude that implementing a PPU within the co-processor is a promising way to speed up the DNN inference phase.

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Section: A Type-i Unumsmentioning

confidence: 99%

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

Cococcioni

Ruffaldi²,

Saponara

2018

2018 International Conference of Electrical and Electronic Technologies for Automotive

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“…In FMCW radar, Q-noise accumulates because the FFT is repeatedly performed during signal processing. Therefore, many studies have proposed designing and implementing the FFT processor using a floating-point operator [ 15 , 16 , 17 , 18 , 19 ].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

Heo

Jung

Lee

et al. 2021

Sensors

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This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

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“…The unum format, so far, has been supported in various programming environments including Julia [7], Matlab [8], Python [9], J and Mathematica [6] languages. Very recently, initial efforts on hardware with unum support focus on early synthesis [10] of three operators (i.e., addition, multiplication, and comparison), and FPGA implementation [11] of four operators (i.e., addition, subtraction, multiplication and division). To clearly evaluate the benefits and challenges of unum hardware design in silicon, we present -to the best of our knowledge -the first ASIC as a fully operational unum processor capable of performing additions and subtractions as well as format-specific functions for lossless and lossy compressions.…”

Section: Introductionmentioning

confidence: 99%

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm

Glaser

Mach

Rahimi

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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To overcome the limitations of conventional floatingpoint number formats, an interval arithmetic and variablewidth storage format called universal number (unum) has been recently introduced [1]. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210 uW/MHz.

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Enhancing Precision and Bandwidth in Cloud Computing: Implementation of a Novel Floating-Point Format on FPGA

Cited by 8 publications

References 7 publications

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm

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