An 826 MOPS, 210uW/MHz Unum ALU in 65 nm

Glaser, Florian; Mach, Stefan; Rahimi, Abbas; Gürkaynak, Frank K.; Huang, Qiuting; Benini, Luca

doi:10.1109/iscas.2018.8351546

Cited by 20 publications

(14 citation statements)

References 9 publications

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“…This architecture only instantiates one coprocessor 4 ○. The coprocessor scratchpad hosts gbounds, and the main memory 5 ○ hosts UNUMs/ubounds. The conversion between those two formats is handled, during load and store operations, by a dedicated Load and Store Unit (LSU, 3 ○).…”

Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

“…The coprocessor is interfaced, through the RoCC interface 4 ○, with the main core (instructions and data ports) and with the memory (cache L1). In 1 ○, the control unit 5 ○ decodes the input instruction and generates the control words for the decode and execute stages. 1 ○ hosts the gbound Register File 6 ○ (gRF, Section 3).…”

Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

“…Only few UNUM type I hardware demonstrators have been built (e.g. [1], [8], [5]) but none of them support multiple UE illustrate how to efficiently store numbers in main memory.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Smurf

Bocco

Durand

Dinechin

2019

Proceedings of the Conference for Next Generation Arithmetic 2019

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This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost. CCS CONCEPTS • Hardware → Emerging technologies; Very large scale integration design; Communication hardware, interfaces and storage; Power and energy; • Computer systems organization → Architectures; Embedded and cyber-physical systems; • Computing methodologies → Modeling and simulation;

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Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

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Smurf

Bocco

Durand

Dinechin

2019

Proceedings of the Conference for Next Generation Arithmetic 2019

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“…In that work, the authors showed a save of 80% of storage space with respect the use of Floats, without loosing in accuracy. • Hardware implementations: Type-I Unums have been recently implemented in hardware, on FPGA [16,22]. The authors conclude that implementing in hardware Type-I Unums requires a bigger area than that of an FPU.…”

Section: A Type-i Unumsmentioning

confidence: 99%

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

Cococcioni

Ruffaldi²,

Saponara

2018

2018 International Conference of Electrical and Electronic Technologies for Automotive

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This paper discusses the introduction of an integrated Posit Processing Unit (PPU) as an alternative to Floating-point Processing Unit (FPU) for Deep Neural Networks (DNNs) in automotive applications. Autonomous Driving tasks are increasingly depending on DNNs. For example, the detection of obstacles by means of object classification needs to be performed in real-time without involving remote computing. To speed up the inference phase of DNNs the CPUs on-board the vehicle should be equipped with co-processors, such as GPUs, which embed specific optimization for DNN tasks. In this work, we review an alternative arithmetic that could be used within the co-processor. We argue that a new representation for floating point numbers called Posit is particularly advantageous, allowing for a better trade-off between computation accuracy and implementation complexity. We conclude that implementing a PPU within the co-processor is a promising way to speed up the DNN inference phase.

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“…We use a Julia-based emulator on a conventional CPU, as posit hardware is not yet available. Posit research currently focuses on hardware implementations [6,7,12,32].…”

mentioning

confidence: 99%

Posits as an alternative to floats for weather and climate models

Klöwer

Dueben

Palmer

2019

Proceedings of the Conference for Next Generation Arithmetic 2019

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Posit numbers, a recently proposed alternative to floating-point numbers, claim to have smaller arithmetic rounding errors in many applications. By studying weather and climate models of low and medium complexity (the Lorenz system and a shallow water model) we present benefits of posits compared to floats at 16 bit. As a standardised posit processor does not exist yet, we emulate posit arithmetic on a conventional CPU. Using a shallow water model, forecasts based on 16-bit posits with 1 or 2 exponent bits are clearly more accurate than half precision floats. We therefore propose 16 bit with 2 exponent bits as a standard posit format, as its wide dynamic range of 32 orders of magnitude provides a great potential for many weather and climate models. Although the focus is on geophysical fluid simulations, the results are also meaningful and promising for reduced precision posit arithmetic in the wider field of computational fluid dynamics.

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An 826 MOPS, 210uW/MHz Unum ALU in 65 nm

Cited by 20 publications

References 9 publications

Smurf

Smurf

Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

Posits as an alternative to floats for weather and climate models

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