Enhancing performance of wireless NoCs with distributed MAC protocols

Duraisamy, Karthi; Kim, Ryan; Pande, Partha Pratim

doi:10.1109/isqed.2015.7085460

Cited by 21 publications

(12 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to efficiently handle this asymmetric traffic, we require an efficient wireless MAC protocol that can dynamically allocate wireless bandwidth between MC-to-GPU and GPU-to-MC data transfers, depending on the current instantaneous communication requirements. For this purpose, we employ the distributed MAC protocol described in [44]. With this MAC, whenever a message wants to utilize the wireless channel, the state of the wireless medium is first checked.…”

Section: Communication Protocolsmentioning

confidence: 99%

“…If WI 2 wants to request the wireless channel, WI 2 broadcasts a 1 during b2 and listens for other requests during b0, b1, and b3. After the request period, all WIs follow a simple fairness-based common node selection algorithm [44]. Following the execution of this node selection algorithm, one of the requesting WIs acquires the wireless channel and starts transmitting data packets.…”

Section: Communication Protocolsmentioning

confidence: 99%

“…As observed from this figure, the EDP initially reduces as the WI count increases: higher number of wireless shortcuts improves the wireless utilization and hence, lowers the overall network latency. However, beyond a WI count of 24, with more than six WIs allocated on a single wireless channel, the MAC overhead (and hence, the channel access latency) and, therefore, the network EDP starts to increase [44]. Hence, in our WiHetNoC, we employ 24 WIs for GPU-MC communication (four channels are used with six WIs operating on each channel).…”

Section: Number Of Wismentioning

confidence: 99%

See 2 more Smart Citations

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

Choi

Duraisamy

Kim

et al. 2018

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

Convolutional Neural Networks (CNNs) have shown a great deal of success in diverse application domains including computer vision, speech recognition, and natural language processing. However, as the size of datasets and the depth of neural network architectures continue to grow, it is imperative to design high-performance and energy-efficient computing hardware for training CNNs. In this paper, we consider the problem of designing specialized CPU-GPU based heterogeneous manycore systems for energy-efficient training of CNNs. It has already been shown that the typical on-chip communication infrastructures employed in conventional CPU-GPU based heterogeneous manycore platforms are unable to handle both CPU and GPU communication requirements efficiently. To address this issue, we first analyze the on-chip traffic patterns that arise from the computational processes associated with training two deep CNN architectures, namely, LeNet and CDBNet, to perform image classification. By leveraging this knowledge, we design a hybrid Network-on-Chip (NoC) architecture, which consists of both wireline and wireless links, to improve the performance of CPU-GPU based heterogeneous manycore platforms running the above-mentioned CNN training workloads. The proposed NoC achieves 1.8× reduction in network latency and improves the network throughput by a factor of 2.2 for training CNNs, when compared to a highly-optimized wireline mesh NoC. For the considered CNN workloads, these network-level improvements translate into 25% savings in full-system energy-delay-product (EDP). This demonstrates that the proposed hybrid NoC for heterogeneous manycore architectures is capable of significantly accelerating training of CNNs while remaining energy-efficient.

show abstract

Section: Communication Protocolsmentioning

confidence: 99%

Section: Communication Protocolsmentioning

confidence: 99%

Section: Number Of Wismentioning

confidence: 99%

See 1 more Smart Citation

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

Choi

Duraisamy

Kim

et al. 2018

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Given the total number of WIs allowed (NWI), we use a WI placement strategy that focuses on minimizing traffic-weighted hop-count [32]. Following this methodology and by varying NWI, we find both the optimum number of wireless interfaces and the best locations in the WiHetNoC.…”

Section: Wireless Link Placementmentioning

confidence: 99%

Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms

Choi

Duraisamy

Kim

et al. 2016

Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Self Cite

View full text Add to dashboard Cite

In recent years, designing specialized manycore heterogeneous architectures for deep learning kernels has become an area of great interest. However, the typical on-chip communication infrastructures employed on conventional manycore platforms are unable to handle both CPU and GPU communication requirements efficiently. Hence, in this paper, our aim is to enhance the performance of heterogeneous manycore architectures through the design of a hybrid NoC consisting of both wireline and wireless links. To this end, we specifically target the resource-intensive backpropagation algorithm commonly used as the training method in deep learning. For backpropagation, the proposed hybrid NoC achieves 1.9X reduction in network latency and improves the network throughput by a factor of 2 with respect to a highly optimized mesh NoC. These network level improvements translate into 25% savings in full system energy-delay-product (EDP). This demonstrates the capability of the proposed hybrid and heterogeneous manycore architecture in accelerating deep learning kernels in an energy-efficient manner.

show abstract

“…However, the CNT based wireless technology used in that work is difficult to integrate in current CMOS process. A distributed MAC protocol is proposed in [14]. The proposed mechanism uses simple orthogonally coded request packets, processing the request packets and granting permission to the channel by a priority based mechanism.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism

Mansoor

Ganguly

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-onChips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.

show abstract

Enhancing performance of wireless NoCs with distributed MAC protocols

Cited by 21 publications

References 10 publications

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms

Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism

Contact Info

Product

Resources

About