Enhancing NIC Performance for MPI using Processing-in-Memory

Rodrigues, Arun F.; Murphy, Richard C.; Brightwell, Ron; Underwood, Keith D.

doi:10.1109/ipdps.2005.203

Cited by 9 publications

(4 citation statements)

References 17 publications

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“…Though not discussed in this paper, our simulation infrastructure already supports both SPLASH2 and NASOpenMP benchmarks [1,2]. We are currently investigating these benchmarks and trying to characterize their behavior in terms of synchronization overheads.…”

Section: Discussionmentioning

confidence: 99%

“…This paper deals with architectures that expose novel concurrency models by using light-weight multithreading and support high computation to memory ratio by leveraging technologies such as Processing-In-Memory (PIM), Embedded DRAM, or Stacked Memory [1,2]. In this paper we explore the idea of implementing key parallel processing functions such as synchronization locks and barriers for one such architecture, namely the Light-Weight Processing (LWP) architecture ( Figure 1).…”

Section: Introductionmentioning

confidence: 99%

“…Support for large number of hardware threads needs to be backed by low overhead synchronization capability. The LWP architecture uses Full/Empty Bits (FEB) [1,2] in memory to support fast producer-consumer communication.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Evaluating synchronization techniques for light-weight multithreaded/multicore architectures

Sridharan

Rodrigues

Kogge

2007

Proceedings of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Evaluating synchronization techniques for light-weight multithreaded/multicore architectures

Sridharan

Rodrigues

Kogge

2007

Proceedings of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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“…Other work has shown that router processing is an efficient means to trigger message initiated execution [22], as well as simply move data. This model does not currently include such facilities, but they may be added later.…”

Section: Hardware Support For Message Triggered Processingmentioning

confidence: 99%

Introducing mNUMA

Vance

Kogge

2010

Proceedings of the Fourth Conference on Partitioned Global Address Space Programming Model

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We describe design details of a LightWeight Processing migration-NUMA architecture, a novel high performance system design that provides hardware support for a partitioned global address space, migrating subjects, and word level synchronization primitives. Using the architectural definition, combinations of structures are shown to work together to carry out basic actions such as address translation, migration, in-memory synchronization, and work management. We present results from simulation of microkernels showing that LWP-mNUMA compensates for latency with far greater memory access concurrency than possible on a conventional systems. In particular, several microkernels model tough, irregular access patterns that have limited speedups -in certain problem areas -to dozens of conventional processors. On these, results show speedup increasing up to 1024 multicore mNUMA processing nodes, running over 1 million threadlets.LightWeight Processing migration-NUMA refers to this synergistic combination of massively parallel lightweight multithreading, migration based consistency, and memory extensions for word level inter-thread synchronization.LWP-mNUMA draws on previous investigation [14] into architectural techniques to support applications which do not map well to distributed memory systems. In the process of mapping graph traversal applications [17] onto a novel architecture [27], a new architecture, programming model, and algorithmic approach emerged simultaneously. This paper presents initial results of this co-design.This paper begins with a description (section 2) of the programming environment supported by mNUMA hardware. Next, the architecture itself is presented in two sections. Section 3 presents major hardware components and memory structures. Then, section 4 explains how these components interact to ensure correct and efficient operation of memory access, thread management, and synchronization. Section 5 presents a set of experimental results. After the reader has seen how mNUMA fits together, section 6 presents related work. Section 7 concludes with summary and future work. Mobile-Subjective Programming ModelAll computation and communication in an mNUMA system occurs by the action of subjects. Subjects are strictly runtime entities, dynamically created from code objects specified by a programmer. Subjectivity results from always placing executing objects in ex-A0

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