Enhancing Memory Window Efficiency of Ferroelectric Transistor for Neuromorphic Computing via Two‐Dimensional Materials Integration

Abstract

In‐memory computing, particularly neuromorphic computing, has emerged as a promising solution to overcome the energy and time‐consuming challenges associated with the von Neumann architecture. The ferroelectric field‐effect transistor (FeFET) technology, with its fast and energy‐efficient switching and nonvolatile memory, is a potential candidate for enabling both computing and memory within a single transistor. In this study, the capabilities of an integrated ferroelectric HfO2 and 2D MoS2 channel FeFET in achieving high‐performance 4‐bit per cell memory with low variation and power consumption synapses, while retaining the ability to implement diverse learning rules, are demonstrated. Notably, this device accurately recognizes MNIST handwritten digits with over 94% accuracy using online training mode. These results highlight the potential of FeFET‐based in‐memory computing for future neuromorphic computing applications.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

“…The corresponding highest recognition accuracy achieved is 95%, which surpasses the performance of most synaptic devices based on three-terminal transistors (Table ). ,,,,,− Moreover, the corresponding mapping-synaptic-weights image (Figure S14d) is distinguishable and closely resembles the pristine image (Figure S14c). We developed a video (Supplementary Video 2) that demonstrates the progressive improvement in the clarity of the face outline, confirming the potential applications of our synaptic device in high-energy-efficient neuromorphic computing systems.…”

Ultra‐Steep‐Slope and High‐Stability of CuInP2S6/WS2 Ferroelectric Negative Capacitor Transistors by Passivation Effect and Dual‐Gate Modulation

“…The hysteresis window can be related to the capacitance mismatch between the ferroelectric layer and the semiconductor channel. [41][42][43] The detailed electrical performance can be found in Figure S7, Supporting Information. The thickness control on WS 2 and Al 2 O 3 has been conducted to optimize the overall performance (see details in Figure S8, Supporting Information), thinner WS 2 channel leads to a larger hysteresis window, while the thicker WS 2 degrades the modulating capability of the 2D ferroelectric CuInP 2 S 6 towards WS 2 .…”

PZT-Enabled MoS2 Floating Gate Transistors: Overcoming Boltzmann Tyranny and Achieving Ultralow Energy Consumption for High-Accuracy Neuromorphic Computing

“…As depicted in Figure h, after training for 150 learning epochs, the recognition accuracy of our ANN reaches 97.3%, which is slightly lower than the recognition accuracy of 98.5% achieved using the ideal software weight updates. Our synaptic device outperforms most synaptic devices based on three-terminal transistors (Table ) ,,,,− in terms of recognition accuracy and weight-updating energy consumption. As shown in panels i–k of Figure , the synaptic weight mapping image (Figure j) of the ideal MLP simulator closely resembles the input pristine image (Figure i).…”