Enhancing FSM traversal by temporary re-encoding

Cabodi, Gianpiero; Camurati, P.; Lavagao, L.; Macii, Enrico; Poncino, Massimo; Quer, Stefano; Sentovich, Ellen M.

doi:10.1109/iccd.1996.563524

Cited by 4 publications

(2 citation statements)

References 10 publications

(5 reference statements)

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“…26 The overall tool includes all recently published dynamic reordering techniques and a traversal method based on a partitioned and clustered transition relation with sorting heuristics and other optimizations. 6,23,27,28,29 Moreover, we also use some optimizations reported in Cabodi et al 20 We use this tool both without and with the improved method based on partitioning: in the former case we consider our tool as 'state-of-the-art', and it servers the purpose of measuring the improvement obtained with our novel technique. Our experiments run on a 200 MHz DEC Alpha with a 256 Mbyte main memory.…”

Section: Resultsmentioning

confidence: 99%

Memory optimization in function and set manipulation with BDDs

Cabodi¹,

Quer²,

Camurati³

1998

Softw: Pract. Exper.

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SUMMARYBinary Decision Diagrams (BDDs) are the state-of-the-art technique for many synthesis, verification and testing problems in CAD for VLSI. Many researchers proposed optimized BDD-based representations, but in many complex applications the (working) memory required is still too much. Virtual memory is no alternative solution, because if the working set size for a program is large and memory accesses are random, an extremely large number of page faults significantly modifies the performance of the software. This paper proposes a solution to this problem for a specific application, namely BDD-based exploration of large state spaces, an issue often found in CAD for VLSI. Our 'divide-and-conquer' approach for reachability analysis is based on decomposition of state sets carried out at different levels and on an effective use of mass memory. As a result, we are able to explore the state space of large Finite State Machines. At the same time, the technique we develop is orthogonal to a variety of symbolic techniques and graph manipulation procedures and it allows reducing complexity of very common operations. Experimental results, on well known synchronous benchmarks usually used in the field of CAD for VLSI, show that this approach is particularly effective on larger problems as decomposition decreases the amount of working memory, avoids page faulting and makes the overall process more efficient.

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Section: Resultsmentioning

confidence: 99%

Memory optimization in function and set manipulation with BDDs

Cabodi¹,

Quer²,

Camurati³

1998

Softw: Pract. Exper.

View full text Add to dashboard Cite

show abstract

Section: Resultsmentioning

confidence: 99%

Memory optimization in function and set manipulation with BDDs

Cabodi

Quer

Camurati³

1998

Softw: Pract. Exper.

View full text Add to dashboard Cite

Binary Decision Diagrams (BDDs) are the state-of-the-art technique for many synthesis, verification and testing problems in CAD for VLSI. Many researchers proposed optimized BDD-based representations, but in many complex applications the (working) memory required is still too much. Virtual memory is no alternative solution, because if the working set size for a program is large and memory accesses are random, an extremely large number of page faults significantly modifies the performance of the software. This paper proposes a solution to this problem for a specific application, namely BDD-based exploration of large state spaces, an issue often found in CAD for VLSI. Our 'divide-and-conquer' approach for reachability analysis is based on decomposition of state sets carried out at different levels and on an effective use of mass memory. As a result, we are able to explore the state space of large Finite State Machines. At the same time, the technique we develop is orthogonal to a variety of symbolic techniques and graph manipulation procedures and it allows reducing complexity of very common operations. Experimental results, on well known synchronous benchmarks usually used in the field of CAD for VLSI, show that this approach is particularly effective on larger problems as decomposition decreases the amount of working memory, avoids page faulting and makes the overall process more efficient.

show abstract