Enhancement-Mode GaN p-Channel MOSFETs for Power Integration

Zheng, Zheyang; Song, Wenlei; Zhang, Li; Yang, Song; Han, Xu; Wong, Roy K.-Y.; Wei, Jin; Chen, Kevin J.

doi:10.1109/ispsd46842.2020.9170081

Cited by 22 publications

(12 citation statements)

References 18 publications

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“…4(a) depicts the output curves of the devices. Owing to the p ++ -GaN cap layer of the epitaxial structure, an offset voltage, which is usually observed in I DS −V DS curves of p-FETs fabricated on the moderate Mg-doped p-GaN layer [31,32] , is effectively eliminated. The O 3 -Al 2 O 3 /HfO 2 -stacked device with better channel modulation capability delivers a high-saturation current density of −4.9 mA/mm and an on-resistance (R on ) of 0.70 kΩ•mm at V GS = −10 V. Three-terminal OFF-state characteristics of the fabricated GaN p-FET is plotted in Fig.…”

Section: Epitaxial Structure and Dielectric Leakage Characterizationmentioning

confidence: 99%

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

Jin,

Huang,

Jiang

et al. 2023

J. Semicond.

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In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

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Section: Epitaxial Structure and Dielectric Leakage Characterizationmentioning

confidence: 99%

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

Jin,

Huang,

Jiang

et al. 2023

J. Semicond.

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“…Fortunately, the GaN power IC technology provides a p-GaN layer that can be used for a p-channel transistor. Already first works realize a p-channel FET and the combination of both transistor types in a GaN CMOS inverter was shown in [94,95]. The current consumption can be massively reduced compared to DCFL inverter and enable a complementary transistor that allow higher energy-efficiency.…”

Section: ) Gan Cmosmentioning

confidence: 99%

Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

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GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as 56.7 µm 2 and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.INDEX TERMS Gallium nitride, integrated circuit technology, power integrated circuits, logic circuits, analog circuits

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“…Several p-channel devices with polarization-induced two-dimensional hole gas (2DHG) at the heterointerface have been reported. − Similar to a 2DEG, the 2DHG has characteristics of high density and temperature independence . However, to achieve a GaN-based complementary metal-oxide-semiconductor (CMOS) technology, p-channel devices with high on-current, enhancement-mode (E-mode), and high on/off ratio are desired to be integrated with a related n-channel power device on the same platform. ,− Recently, due to the commercialization of E-mode p-GaN gate high electron mobility power transistors (HEMTs), p-channel MOSFETs (pFETs) with the same p-GaN/AlGaN/GaN-based epitaxial structure have attracted great interest. − Among them, E-mode pFETs with ( I ON / I OFF ) of 3 × 10 8 and a high threshold voltage ( V th ) of | – 2.2 V| were demonstrated . However, the improved on-current ( I ON ) of 18.5 mA/mm by 1.5 nm AlN spacer is still much lower than that of a generic E-mode n-channel device .…”

Section: Introductionmentioning

confidence: 99%

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN

Zhou

Binh

Souza

2023

ACS Appl. Electron. Mater.

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The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off ptype metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) pchannel is investigated. In simulations, a scaled p-channel GaN device with L G = 200 nm, L SD = 600 nm achieves an I ON of 65 mA/ mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, I ON /I OFF of ∼10 12 , and |V th | of | − 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of I ON induced by the p-GaN gate resulting in an I ON of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive V th shift.

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Enhancement-Mode GaN p-Channel MOSFETs for Power Integration

Cited by 22 publications

References 18 publications

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

Building Blocks for GaN Power Integration

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN

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Enhancement-Mode GaN p-Channel MOSFETs for Power Integration

Cited by 22 publications

References 18 publications

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

Building Blocks for GaN Power Integration

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN

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Product

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High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric