Enhanced pipelined architecture of H.264/AVC intra prediction

Guo, Jiefeng; Yang, Zhengming; Zheng, Jianmin; Guo, Donghui

doi:10.1016/j.image.2015.11.009

Cited by 2 publications

(1 citation statement)

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“…Another power‐efficient architecture for variable‐sized motion estimation is proposed in the work of Çelebi et al 11 This work achieves it by enabling or disabling the current block and reference block memories. Guo et al 12 proposed a pipelined architecture for H.264/AVC intra prediction. Zhou et al 13 proposed a method to reduce the complexity of bidirectional motion estimation by switching the use of small and large search ranges.…”

Section: Introductionmentioning

confidence: 99%

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

Chandran

Chandramani

2019

Concurrency and Computation

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Summary Motion estimation is the important and computationally intensive part of any video encoding. The objective of this paper is to design and analyze the coarse and fine reconfiguration of processing element‐based hardware design for block matching–based motion estimation in H.265/HEVC video processing. Sum of absolute difference (SAD) is the commonly used criteria for block matching in the motion estimation process. User input is taken as the parameter for coarse reconfiguration, and the threshold value in SAD is considered for the fine reconfiguration. Processing elements are the hardware units designed for performing SAD calculation. In this work, the hardware for block‐based motion estimation for H.265/HEVC encoder is designed using multiple processing elements, which will calculate the SAD values. A system‐on‐chip architecture is implemented and verified the optimization in terms of power and area utilization by reconfiguring the architecture dynamically based on the input video quality requirement.

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Section: Introductionmentioning

confidence: 99%

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

Chandran

Chandramani

2019

Concurrency and Computation

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Entropy Coding for H.264 Video Compression

Patil¹,

Nandyal²

2022

ijsr

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H.264/AVC standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The H.264/AVC standardization is now achieving signicant improvement in rate-distortion efciency for digital systems worldwide. This paper provides an overview of the technical features of H.264/AVC, describing its baseline proles, motion estimation for inter, and intra prediction. To improve the human perceptual quality of videos deblocking lter and perceptual quality assessments are described in detail.

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Enhanced pipelined architecture of H.264/AVC intra prediction

Cited by 2 publications

References 20 publications

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

Entropy Coding for H.264 Video Compression

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